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NTH+5V PDF预览

NTH+5V

更新时间: 2022-01-20 21:36:00
品牌 Logo 应用领域
其他 - ETC 振荡器
页数 文件大小 规格书
3页 303K
描述
Oscillators | HCMOS/TTL Comp

NTH+5V 数据手册

 浏览型号NTH+5V的Datasheet PDF文件第2页浏览型号NTH+5V的Datasheet PDF文件第3页 
SaRonix  
Crystal Clock Oscillator  
5V, HCMOS  
NTH / NCH Series  
Technical Data  
Frequency Range:  
500 kHz to 106.25 MHz  
20*, 25, 50 or 100 ꢀꢀm over all conditionsꢁ calibration  
Frequency Stability:  
tolerance, oꢀerating temꢀerature, inꢀut voltage change, load  
change, 30 day aging, shock and vibration.  
*See Part Numbering Guide  
Temperature Range:  
Oꢀeratingꢁ  
Storageꢁ  
0 to +70°C or -40 to +85°C  
-55 to +125°C  
Supply Voltage:  
Recommended Oꢀeratingꢁ  
+5VDC 10%  
0.5 to 8 MHzꢁ  
8+ to 24 MHzꢁ  
24+ to 50 MHzꢁ  
50+ to 80 MHz  
12mA  
20mA  
35mA  
50mA  
65mA  
Supply  
Current:  
ACTUAL SIZE  
80+ to 106.25 MHzꢁ  
Description  
Output Drive:  
Symmetryꢁ  
Rise & Fall Timesꢁ  
measured @ 50%V  
8ns max, 0.5 to 24 MHz, 20% to 80% V  
5ns max, 24+ to 80 MHz  
See Part Numbering Guide  
DD,  
HCMOS  
A 5V crystal controlled, low current, low  
jitter and high frequency oscillator with  
ꢀrecise rise and fall times demanded in  
networking aꢀꢀlications, such as Gigabit  
EthernetandFibreChannel. Thetri-state  
function on the NTH enables the outꢀut  
to go high imꢀedance. Device is ꢀack-  
aged in a 14 or an 8-ꢀin DIP comꢀatible  
resistance welded, all metal grounded  
case, to reduce EMI. True SMD DIL 14  
version also available, utilizing new  
adaꢀtor technology (see seꢀarate data  
sheet for ꢀackage dimensions)  
DD  
2ns max, 80+ to 106.25 MHz  
Logic 0ꢁ  
Logic 1ꢁ  
Loadꢁ  
10% V  
90% V  
max  
min  
DD  
DD  
50ꢀF to 50MHz, 30ꢀF 50+ to 70 MHz, 15ꢀF 70+ to 106.25 MHz  
8ꢀs max  
RMS Period Jitterꢁ  
TTL  
Symmetryꢁ  
Rise & Fall Timesꢁ  
measured @ 1.5V level, See Part Numbering Guide  
6ns max, 0.5 to 24 MHz, 0.5 to 2.5V  
3ns max, 24+ to 80 MHz  
1.5ns max, 80+ to 106.25 MHz  
0.5V max  
Logic 0ꢁ  
Logic 1ꢁ  
Loadꢁ  
V
-0.6V min  
CC  
10TTL to 50MHz, 5TTL 50+ to 106.25 MHz  
8ꢀs max  
RMS Period Jitterꢁ  
Applications & Features  
Mechanical:  
• ADSL, DSL  
Shockꢁ  
Solderabilityꢁ  
Terminal Strengthꢁ  
Vibrationꢁ  
Solvent Resistanceꢁ  
MIL-STD-883, Method 2002, Condition B  
MIL-STD-883, Method 2003  
MIL-STD-883, Method 2004, Conditions B2  
MIL-STD-883, Method 2007, Condition A  
MIL-STD-202, Method 215  
• DS3, ES3, E1, STS-1, T1  
• Ethernet Switch, Gigabit Ethernet  
• Fibre Channel Controller  
• MPEG  
Resistance to Soldering Heatꢁ  
MIL-STD-202, Method 210, Condition A, B or C  
( I or J for Gull Wing and SMD)  
• Network Processors  
• Voice Over Packet  
• 32 Bit Microꢀrocessors  
• Tri-State outꢀut on NTH  
• True SMD version available, see ꢀart  
number builder for ꢀackage oꢀtion  
Environmental:  
Gross Leak Testꢁ  
Fine Leak Testꢁ  
Thermal Shockꢁ  
MIL-STD-883, Method 1014, Condition C  
MIL-STD-883, Method 1014, Condition A2  
MIL-STD-883, Method 1011, Condition A  
MIL-STD-883, Method 1004  
Moisture Resistanceꢁ  
Output Waveform  
Tri-State Logic Table (NTH only)  
CMOS  
TTL  
Pin 1 Input  
Logic 1 or NC  
Logic 0 or GND  
Pin 8 (5) Output  
Required Input Levels on Pin 1:  
Logic 1 = 3.0 V min  
Logic 0 = 0.5V max  
T
T
T
T
f
r
f
r
Oscillation  
V
1 Level  
DD  
High Impedance  
80% V  
DD  
DD  
Outꢀutꢁ  
Oscillation @ V , 2.2V min  
IN  
High Imꢀedance @ V , 0.8V max  
IN  
50Kmin  
Disable Outꢀut Delayꢁ 100ns max  
50% V  
20% V  
2.5 VDC  
1.5 VDC  
0.5 VDC  
Outꢀutꢁ  
Internal Pulluꢀ Resistance  
Control Inꢀutꢁ  
DD  
0 Level  
GND  
SYMMETRY  
SYMMETRY  
DS-104 REV F  
141 Jefferson Drive • Menlo Park, CA 94303 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894  
SaRonix  

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