Datasheet > NT3960

NT3960

更新时间： 2022-11-28 10:00:42

品牌	Logo	应用领域
其他 - ETC		驱动器
页数	文件大小	规格书
20页	226K
描述
TFT LCD Source Driver

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NT3960 数据手册

NT3960

TFT LCD Source Driver

Pad Description

Pad No.

Description

Designation I/O

132~140,142~150, D05 ~ D00

112~120,122~130, D15 ~ D10

Data input. For three 6-bit data,1 pixel, of color data (R, G, B)

DX5 : MSB; DX0 : LSB

47~55, 57~65

31 ~ 34

D25 ~ D20

REV

Controls whether data is inverted or not.

When “REV”=1 the data will be inverted. EX. “00” ꢁ“ 3F”, “07”ꢁ“ 38”, “15”ꢁ“2A”,

and so on.

152 ~ 155

69 ~ 71

CLK

Clock signal; latching data onto the line latches at the rising edge.

SELT

Selects the output channel number; when SELT= “0” : 309 channels; and “1” = 300

channels (OUT151~ OUT159 are in-available ). There is a 100K internal pull-up

resistor with this pin.

106 ~ 77

V1 ~ V10

Gamma correction reference voltage. The voltage of these pins must be AVSS<

V10< V9< V8<V7<V6; V5<V4<V3<V2<V1< AVDD

189 ~ 497

OUT1 ~

OUT309

Output drive signals;

If 300-channel function is selected, OUT151~ OUT159 are in-available.

Selects left or right shift;

35 ~ 37

SHL

SHL=“1” : DIO1ꢁOUT1,2,3ꢁOUT4,5,6ꢁOUT7,8,9---ꢁOUT307,308,309= DIO2

SHL=“0” : DIO1=OUT1,2,3ꢂOUT4,5,6ꢂOUT7,8,9ꢂ--- OUT307,308,309ꢂDIO2

SHL

DIO1

Input

DIO2

Output

Input

SHIFT

Right

Left

Output

176 ~ 178

8 ~ 10

DIO1

DIO2

I/O Start pulse signal input/output

When SHL is applied high (SHL="1"), a start high-pulse on DIO1 is latched at the

rising edge of the CLK. Then the data are latched serially onto internal latches at

the rising edge of the CLK. After all line latches are full with data, 100/103 clocks, a

pulse is shifted out through the DIO2 pin at the rising edge of the CLK. This function

can cascade two or more devices for dot expansion. In normal applications, the

DIO2 signal of the first device is connected to the DIO1 of the second stage, and the

DIO2 of the second one is connected to the DIO1 of the third, and so on like a daisy

chain.

In contrast, when SHL is applied low, a start pulse inputs on DIO2, and outputs

through DIO1.

*Remark : The input pulse-width of DIO1/2 may be over 1 clock-cycle.

Latches the polarity of outputs and switches the new data to outputs.

1. At the rising edge, latches the “POL” signal to control the polarity of the outputs.

44 ~ 46

2. The pin also controls the switch of the line registers that switches the new

incoming data

to outputs.

*Remark : The LD may switch the new data to outputs at anytime even if the line

data are not completely full.

1 234 5 6 7...20

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