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NM34C02EMT8X PDF预览

NM34C02EMT8X

更新时间: 2024-02-20 22:17:50
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飞兆/仙童 - FAIRCHILD /
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12页 94K
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NM34C02EMT8X 数据手册

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March 1999  
NM34C02  
2K-Bit Standard 2-Wire Bus Interface  
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence  
Detect Application on Memory Modules  
General Description  
Features  
The NM34C02 is 2048 bits of CMOS non-volatile electrically  
erasable memory. It is designed to support Serial Presence  
Detect circuitry in memory modules. This communications proto-  
col uses CLOCK (SCL) and DATA I/O (SDA) lines to synchro-  
nously clock data between the master (for example a micropro-  
cessor) and the slave EEPROM device(s).  
Extended Operating Voltage: 2.7V-5.5V  
Write-Protection for first 128 bytes  
200 µA active current typical  
– 10 µA standby current typical  
– 1.0 µA standby current typical (L)  
– 0.1 µA standby current typical (LZ)  
The contents of the non-volatile memory allows the CPU to  
determine the capacity of the module and the electrical character-  
istics of the memory devices it contains. This will enable "plug and  
play" capability as the module is read and PC main memory  
resources utilized through the memory controller.  
IIC compatible interface  
– Provides bidirectional data transfer protocol  
Sixteen byte page write mode  
– Minimizes total write time per byte  
The first 128 bytes of the memory of the NM34C02 can be  
permanentlyWriteProtectedbywritingtothe"WRITEPROTECT"  
Register. Write Protect implementation details are described  
under the section titled Addressing the WP Register.  
Self timed write cycle  
- Typical write cycle time of 6ms  
Endurance: 1,000,000 data changes  
Data retention greater than 40 years  
The NM34C02 is available in a JEDEC standard TSSOP package  
for low profile memory modules for systems requiring efficient  
space utilization such as in a notebook computer. Two options are  
available: L - Low Voltage and LZ - Low Power, allowing the part  
to be used in systems where battery life is of primary importance.  
Packages available: 8-pin TSSOP and 8-pin SO  
Block Diagram  
V
CC  
V
SS  
H.V. GENERATION  
TIMING &CONTROL  
START CYCLE  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER &  
COMPARATOR  
2
E
PROM  
16  
ARRAY  
16 x 16 x 8  
XDEC  
SCL  
LOAD  
INC  
A2  
A1  
A0  
WORD  
ADDRESS  
COUNTER  
0/1/2/3  
4
16  
4
R/W  
YDEC  
Device Address Bits  
8
Write Protect  
Register  
CK  
D
OUT  
DATA REGISTER  
D
IN  
DS012821-1  
1
© 1999 Fairchild Semiconductor Corporation  
NM34C02 Rev. D.2  
www.fairchildsemi.com  

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