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NAND512R3M0AZC5F PDF预览

NAND512R3M0AZC5F

更新时间: 2024-02-03 11:34:32
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存存储内存集成电路动态存储器
页数 文件大小 规格书
23页 229K
描述
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP

NAND512R3M0AZC5F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PBGA-B107
内存集成电路类型:MEMORY CIRCUIT混合内存类型:FLASH+SDRAM
端子数量:107最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA107,10X14,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
电源:1.8 V认证状态:Not Qualified
子类别:Other Memory ICs标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

NAND512R3M0AZC5F 数据手册

 浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第2页浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第3页浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第4页浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第5页浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第6页浏览型号NAND512R3M0AZC5F的Datasheet PDF文件第7页 
NAND256-M  
NAND512-M, NAND01G-M  
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND  
Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP  
Features  
Multi-Chip Packages  
FBGA  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash + 1 die of 256 Mb (x16) SDR  
LPSDRAM  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash + 2 dice of 256 Mb (x16) SDR  
LPSDRAMs  
TFBGA107 10.5 x 13 x 1.2mm  
TFBGA149 10 x 13.5 x 1.2mm  
LFBGA137 10.5 x 13 x 1.4mm  
TFBGA137 10.5 x 13 x 1.2 mm(1)  
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND  
Flash +1 die of 256 Mb (x16) DDR  
LPSDRAM  
– 1 die of 512 Mb (x16) NAND Flash + 1 die  
of 256 Mb or 512 Mb (x16) DDR LPSDRAM  
Supply voltages  
(1) Preliminary specifications.  
– V  
– V  
= 1.7V to 1.95V or 2.5V to 3.6V  
DDF  
DDD  
Fast Block Erase  
= V  
= 1.7V to 1.9V  
DDQD  
– Block erase time: 2ms (typ)  
Electronic Signature  
®
Status Register  
ECOPACK packages  
Data integrity  
Temperature range  
– 100,000 Program/Erase cycles  
– 10 years Data Retention  
– -30 to 85°C  
Flash Memory  
LPSDRAM  
NAND Interface  
Interface: x16 or x 32 bus width  
Deep Power Down mode  
1.8v LVCMOS interface  
– x8 or x16 bus width  
– Multiplexed Address/ Data  
Page size  
– x8 device: (512 + 16 spare) Bytes  
– x16 device: (256 + 8 spare) Words  
Quad internal Banks controlled by BA0 and  
BA1  
Automatic and controlled Precharge  
Block size  
– x8 device: (16K + 512 spare) Bytes  
– x16 device: (8K + 256 spare) Words  
Auto Refresh and Self Refresh  
– 8,192 Refresh cycles/64ms  
– Programmable Partial Array Self Refresh  
Page Read/Program  
– Auto Temperature Compensated Self  
Refresh  
– Random access: 15µs (max)  
– Sequential access: 50ns (min)  
– Page program time: 200µs (typ)  
Wrap sequence: sequential/interleave  
Burst Termination by Burst Stop command and  
Copy Back Program mode  
Precharge command  
– Fast page copy without external buffering  
August 2006  
Rev 5  
1/23  
www.st.com  
2

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