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N80C51BHP

更新时间： 2024-02-14 14:00:25
品牌 Logo 应用领域
英特尔 - INTEL 时钟微控制器外围集成电路装置
页数 文件大小 规格书
21页 278K
描述
Microcontroller, 8-Bit, MROM, 8051 CPU, 12MHz, CMOS, PQCC44, PLASTIC, LCC-44

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N80C51BHP 技术参数

生命周期：Contact Manufacturer包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.75具有ADC：NO
其他特性：BOOLEAN PROCESSOR; ON-CIRCUIT EMULATION地址总线宽度：16
位大小：8DAC 通道：NO
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQCC-J44长度：16.6 mm
I/O 线路数量：32端子数量：44
PWM 通道：NO封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIERROM可编程性：MROM
座面最大高度：4.57 mm表面贴装：YES
技术：CMOS端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：16.6 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

N80C51BHP 数据手册

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87C51/80C51BH/80C31BH  
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER  
Commercial/Express  
87C51/80C51BH/80C51BHP/80C31BH  
*See Table 1 for Proliferation Options  
Y
Y
Y
Y
High Performance CHMOS EPROM  
24 MHz Operation  
5 Interrupt Sources  
Y
Y
Programmable Serial Port  
Improved Quick-Pulse Programming  
Algorithm  
TTL- and CMOS-Compatible Logic  
Levels  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
3-Level Program Memory Lock  
Boolean Processor  
64K External Program Memory Space  
64K External Data Memory Space  
ONCE Mode Facilitates System Testing  
128-Byte Data RAM  
32 Programmable I/O Lines  
Two 16-Bit Timer/Counters  
Extended Temperature Range  
Power Control Modes  
Ð Idle  
Ð Power Down  
b
a
40 C to 85 C)  
(
§
§
MEMORY ORGANIZATION  
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In  
addition the device can address up to 64K of program memory external to the chip.  
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of  
external data memory.  
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on  
a member of the MCS 51 controller family, the  
Intel’s reliable CHMOS III-E technology. Being  
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-  
pin compatible with the existing MCS 51 controller family of products.  
É
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64  
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code  
protection and at the same time allows code verification.  
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make  
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,  
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the  
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.  
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,  
unless information applies to a specific device.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1995  
October 1995  
Order Number: 272335-003  
1234567...21

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