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MX9691 PDF预览

MX9691

更新时间: 2024-02-21 16:18:45
品牌 Logo 应用领域
旺宏电子 - Macronix 数据传输PC外围集成电路
页数 文件大小 规格书
26页 125K
描述
Flash Memory Drive, 1MBps, CMOS, PQFP128, TQFP-128

MX9691 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP128(UNSPEC)
针数:128Reach Compliance Code:unknown
风险等级:5.92其他特性:IT ALSO OPERATES AT 5V SUPPLY; IT SUPPORTS 1KB INTERNAL RAM
驱动器接口标准:IDE外部数据总线宽度:16
主机数据传输速率最大值:20 MBps主机接口标准:PCMCIA-ATA
JESD-30 代码:S-PQFP-G128JESD-609代码:e0
长度:14 mm端子数量:128
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128(UNSPEC)封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:1.45 mm子类别:Bus Controllers
最大压摆率:40 mA最大供电电压:3.5 V
最小供电电压:3.1 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmuPs/uCs/外围集成电路类型:SECONDARY STORAGE CONTROLLER, FLASH MEMORY DRIVE
Base Number Matches:1

MX9691 数据手册

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INDEX  
MX9691  
GENERAL DESCRIPTION  
The Macronix's Solid State Disk controller is fully inte-  
grated flash memory controller that provides all the con-  
trol logic for a PC Card ATA flash memory. The MX9691  
combines 1KB dual-port buffer and buffer manager, inte-  
grated MX93011 DSP core , and a complete host inter-  
face for both the PC Card ATA and ATA standard.  
trol signals to execute read/write/erase operation for flash  
memory chip.  
The MX9691 is fully compliant with the PC Card ATA  
specification.It includes 256 bytes of integrated attribute  
memory(for the required Card Information Structure) and  
four Card Configuration registers. The PCMCIA device  
driver can access the MX9691 ATA command block  
through four different modes by writing the different modes  
by writing the configuration index of the attribute memory  
configuration option register.  
The MX9691 is typically configured with up to  
32MB(unformatted) capacity for 16 pcs. 16Mbit flash  
memory or 64MB(unformatted) capacity for 16 pcs.  
32Mbit flash memory.The MX9691 supports all the con-  
PIN DESCRIPTION  
Host Interface  
Symbol  
No.  
Type  
I
Description  
HA[10:0]  
92,94, 96-97,  
99,101-103,  
106,109,113  
Host address line 10-0.  
These pins include internal pull-up resistors.  
HD[15:0]  
84-89,116-117, I/O  
121-128  
Host data line 15-0.  
These pins include internal bus holder circuit that keep previous state  
when tri-state.  
HOE#,HWE# 104,111  
I
I
I
Host memory read/write/mode select : Both pins include internal pull-  
up resistors that is default in PCMCIA mode.  
Host I/O access.  
IOR#,IOW#  
107,110  
100  
Both pins include internal pull-up resistors.  
HRESET/  
HRESET#  
The host reset signal, when active, initializes the control/status  
registers and stops any command in process.In PCMCIA mode, the  
signal is active high. In ATA extension mode, this signal is active low.  
This signal include internal pull-down resistor.  
WAIT/  
98  
O,OD WAIT or INPUT CHANNEL READY : In both PCMCIA and ATA  
extension modes, this signal holds host transfers until the controller is  
ready to respond.  
IOCHRDY  
RDY/BSY#/  
IREQ#/  
119  
O,Z  
READY/BUSY or HOST INTERRUPT : In PCMCIA mode, this signal  
has two functions. In PCMCIA common memory mode, this signal is  
ready/busy.It is asserted busy by the reset logic, and can be deasserted  
by the local uC. In PCMCIA I/O mode, this signal is IREQ#. In ATA  
extension mode, this active high signal is HOSTINT, which, when  
enable, send an interrupt to the host.  
HOSTINT  
2

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