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MU9C5640LF-70TZC PDF预览

MU9C5640LF-70TZC

更新时间： 2024-02-03 21:14:50
品牌 Logo 应用领域
MUSIC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
22页 185K
描述
Content Addressable SRAM, 256X64, 70ns, CMOS, PQFP32

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MU9C5640LF-70TZC 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：QFP, QFP32,.35SQ,32Reach Compliance Code：unknown
风险等级：5.8最长访问时间：70 ns
JESD-30 代码：S-PQFP-G32内存密度：16384 bit
内存集成电路类型：CONTENT ADDRESSABLE SRAM内存宽度：64
湿度敏感等级：3端子数量：32
字数：256 words字数代码：256
最高工作温度：70 °C最低工作温度：
组织：256X64封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.002 A子类别：SRAMs
最大压摆率：0.03 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
Base Number Matches：1

MU9C5640LF-70TZC 数据手册

 浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第4页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第5页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第6页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第8页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第9页浏览型号MU9C5640LF-70TZC的Datasheet PDF文件第10页 
Operational Characteristics  
LIST-XL Family  
Cycle Type /E /CM /W I/O Status SPS SPD TCO Operation  
Notes  
Cmd Write  
L
L
L
IN  
IN  
IN  
IN  
Load Instruction decoder  
Load Address register  
Load Control register  
1
2,3  
3
3
3
3
Load Segment Control register  
3
Cmd Read  
L
L
H
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
3
3
Read Next Free Address register  
Read Address register  
Read Status Register bits 15–0  
Read Status Register bits 31–16  
Read Control register  
3
3
4
5
3
3
3
3
Read Segment Control register  
Read Current Persistent Source or Destination  
3
3,10  
Data Write  
Data Read  
L
H
L
IN  
IN  
IN  
IN  
IN  
IN  
3
3
3
3
3
3
Load Comparand register  
Load Mask Register 1  
Load Mask Register 2  
Write Memory Array at address  
Write Memory Array at Next Free address  
Write Memory Array at Highest-Priority match  
6,9  
7,9  
7,9  
7,9  
7,9  
7,9  
L
H
X
H
X
OUT  
OUT  
OUT  
OUT  
OUT  
3
3
3
3
3
Read Comparand register  
Read Mask Register 1  
Read Mask Register 2  
Read Memory Array at address  
Read Memory Array at Highest-Priority match  
6, 9  
8, 9  
8, 9  
8, 9  
7, 8  
H
HIGH-Z  
Deselected  
Table 3: Input/Output Operations  
Notes:  
1.  
2.  
Default Command Write cycle destination (does not require a TCO instruction).  
Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the instruction loaded in the  
previous cycle.  
3.  
Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write or Read cycle only.  
NFA register can not be loaded this way.  
4.  
5.  
Default Command Read cycle source (does not require a TCO instruction).  
Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of Status Register Bits 15–0.  
If next cycle is not a Command Read cycle, any subsequent Command Read cycle accesses the Status Register Bits 15–0.  
Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations, SPD CR or SPS CR restores  
the Comparand register as the destination or source.  
6.  
7.  
8.  
9.  
Selected by executing a Select Persistent Destination instruction.  
Selected by executing a Select Persistent Source instruction.  
Access may require multiple 16-bit Read or Write cycles. The Segment Control register controls the selection of the desired 16-bit segment(s) by  
establishing the Segment counters’ start and end limits and count values.  
10. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a persistent source or  
destination. The TCO PS instruction also reads back the Device ID.  
Control Register Bits CT3 and CT2 set the Address register  
to automatically increment or decrement (or not change)  
during sequences of Command or Data cycles. The Address  
register will change after executing an instruction that  
includes M@[AR] or M@aaaH, or after a data access to the  
end limit segment (as set in the Segment Control register)  
when the persistent source or destination is M@[AR] or  
M@aaaH.  
andonlythe activeAddress register will be writtento orread  
from.  
Next Free Address Register (NF)  
The LIST-XL automatically stores the address of the first  
empty memory location in the Next Free Address register,  
which is then used as a memory address pointer for M@NF  
operations. The Next Free Address register, shown in Table  
9 on page 16, can be read using a TCO NF instruction. After  
a reset, the Next Free Address register is set to zero.  
Either the Foreground or Background Address register will  
be active, depending on which register set has been selected,  
Rev. 3.1  
7
1...45678910...22

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