Datasheet > MT91L62AS

MT91L62AS

更新时间： 2024-01-04 15:16:21

品牌	Logo	应用领域
MITEL		解码器编解码器
页数	文件大小	规格书
17页	81K
描述
ISO2-CMOS 3 Volt Single Rail Codec

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技术参数
数据手册

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MT91L62AS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.36
Is Samacsys：	N	压伸定律：	A/MU-LAW
滤波器：	YES	最大增益公差：	1.6 dB
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e0
长度：	25.195 mm	线性编码：	NOT AVAILABLE
功能数量：	1	端子数量：	20
工作模式：	SYNCHRONOUS/ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	225	电源：	3 V
认证状态：	Not Qualified	座面最大高度：	5.33 mm
子类别：	Codecs	最大压摆率：	0.01 mA
标称供电电压：	3 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	PROGRAMMABLE CODEC
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.62 mm	Base Number Matches：	1

MT91L62AS 数据手册

Advance Information

MT91L62

Companding law selection for the Filter/Codec is

provided by the A/µ companding control pin. Table

1 illustrates these choices.

Overview

The 3V Single-Rail Codec features complete Analog/

Digital and Digital/Analog conversion of audio

signals (Filter/Codec) and an analog interface to a

standard analog transmitter and receiver (analog

Interface). The receiver ampliﬁer is capable of

driving a 20k ohm load.

ITU-T (G.711)

Code

µ-Law

A-Law

+ Full Scale

+ Zero

1000 0000

1111 1111

0111 1111

1010 1010

1101 0101

0101 0101

-Zero

Functional Description

(quiet code)

- Full Scale

0000 0000

0010 1010

Filter/Codec

Table 1: Law Selection

The Filter/Codec block implements conversion of the

analog 0-3.3 kHz speech signals to/from the digital

domain compatible with 64 kb/s PCM B-Channels.

Selection of companding curves and digital code

assignment are programmable. These are ITU-T

G.711 A-law or µ-Law, with true-sign/Alternate Digit

Inversion.

Analog Interfaces

Standard interfaces are provided by the MT91L62.

These are:

• The analog inputs (transmitter), pins AIN+/AIN-.

The maximum peak to peak input is 2.123Vpp

µ−law across AIN+/AIN-

The Filter/Codec block also implements a transmit

audio path gain in the analog domain. Figure 3

depicts the nominal half-channel for the MT91L62.

and 2.2Vpp A-law

across these pins.

• The analog outputs (receiver), pins AOUT+/

AOUT-.This internally compensated fully

differential output driver is capable of driving a

load of 20k ohms.

The internal architecture is fully differential to provide

the best possible noise rejection as well as to allow a

wide dynamic range from a single 3 volt supply

design. This fully differential architecture is

continued into the Analog Interface section to

provide full chip realization of these capabilities for

the external functions.

PCM Serial Interface

A serial link is required to transport data between the

MT91L62 and an external digital transmission

device. The MT91L62 utilizes the strobed data

interface found on many standard Codec devices.

This interface is commonly referred to as Simple

Serial Interface (SSI).

A reference voltage (V ), for the conversion

Ref

requirements of the Codec section, and a bias

voltage (V

), for biasing the internal analog

Bias

sections, are both generated on-chip. V

is also

Bias

brought to an external pin so that it may be used for

biasing external gain setting ampliﬁers. A 0.1µF

The bit clock rate is selected by setting the CSL2-0

control pins as shown in Figure 2.

capacitor must be connected from V

to analog

may only

Bias

ground at all times. Likewise, although V

Ref

be used internally, a 0.1µF capacitor from the V

Ref

Quiet Code

pin to ground is required at all times. The analog

ground reference point for these two capacitors must

be physically the same point. To facilitate this the

The PCM serial port can be made to send quiet code

to the decoder and receive ﬁlter path by setting the

RxMute pin high. Likewise, the PCM serial port will

send quiet code in the transmit path when the

and V

pins are situated on adjacent pins.

Ref

Bias

The transmit ﬁlter is designed to meet ITU-T G.714

speciﬁcations. An anti-aliasing ﬁlter is included. This

is a second order lowpass implementation with a

corner frequency at 25 kHz.

The receive ﬁlter is designed to meet ITU-T G.714

speciﬁcations. Filter response is peaked to

compensate for the sinx/x attenuation caused by the

8 kHz sampling rate.

7-175

1 234 5 6 7...17

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