SRAM
MT5C2568
Austin Semiconductor, Inc.
32K x 8 SRAM
PIN ASSIGNMENT
(Top View)
SRAM MEMORY ARRAY
28-PIN SOJ (ECJ)
28-Pin DIP (C, CW)
32-Pin LCC (ECW)
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-88662
•MIL-STD-883
VCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0 10
DQ1 11
DQ2 12
DQ3 13
1
2
3
4
5
6
7
8
9
28
4
3 2 1 32 31 30
27 WE\
26 A13
25 A8
5
6
7
8
9
10
11
12
13
A6
A5
A4
A3
A2
A1
A0
NC
DQ1
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE\
A10
CE\
DQ8
DQ7
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
FEATURES
• Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS double-metal process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
14 15 16 17 18 19 20
VSS
14
28-Pin LCC (EC)
OPTIONS
• Timing
MARKING
3
2 1 28 27
28-Pin Flat Pack (F)
12ns access1
15ns access1
20ns access
25ns access
35ns access
45ns access
55ns access2
70ns access2
100ns access
-12
-15
-20
-25
-35
-45
-55
-70
-1004
4
5
6
7
8
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
26
25
24
23
22
21
20
19
18
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
VCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0 10
DQ1 11
DQ2 12
DQ3 13
1
2
3
4
5
6
7
8
9
28
27 WE\
26 A13
25 A8
24 A9
9
23 A11
22 OE\
21 A10
20 CE\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
10
11
12
13 14 15 16 17
VSS
14
• Package(s)3
Ceramic DIP (300 mil)
Ceramic DIP (600 mil)
Ceramic LCC (28 leads)
Ceramic LCC (32 leads)
Ceramic Flat Pack
Ceramic SOJ
C
No. 108
GENERAL DESCRIPTION
CW
EC
ECW
F
No. 110
No. 204
No. 208
No. 302
No. 500
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
ECJ
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
• Operating Temperature Ranges
Military -55oC to +125oC
Industrial -40oC to +85oC
XT
IT
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when dis-
abled. This allows system designs to achieve low standby
power requirements.
The “L” version provides a battery backup/low volt-
age data retention mode, offering 2mW maximum power dissi-
pation at 2 volts. All devices operate from a single +5V power
supply and all inputs and outputs are fully TTL compatible.
• 2V data retention/low power
L
NOTES:
1. -12 and -15 available in IT only.
2. Electrical characteristics identical to those provided for the
45ns access devices.
3. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.
4. Available in CW, ECW, and F packages only.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2568
Rev. 1.0 9/99
1