4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
GENERALDESCRIPTION
Th e Micron ® Syn cBurst™ SRAM fam ily em ploys
h igh -speed, low-power CMOS design s th at are fabri-
cated usin g an advan ced CMOS process.
in tern ally gen erated as con trolled by th e burst advan ce
in put (ADV#).
Address an d write con trol are registered on -ch ip to
sim plify WRITE cycles. Th is allows self-tim ed WRITE
cycles. In dividual byte en ables allow in dividual bytes
to be written . Durin g WRITE cycles on th e x18 device,
BWa# con trols DQa pin s an d DQPa; BWb# con trols
DQb pin s an d DQPb. Durin g WRITE cycles on th e x32
an d x36 devices, BWa# con trols DQa pin s an d DQPa;
BWb# con trols DQb pin s an d DQPb; BWc# con trols
DQc pin s an d DQPc; BWd# con trols DQd pin s an d
DQPd. GW# LOW causes all bytes to be written . Parity
bits are on ly available on th e x18 an d x36 version s.
Micron ’s 4Mb Syn cBurst SRAMs operate from a
+3.3V VDD power supply, an d all in puts an d outputs are
TTL-com patible. Users can ch oose eith er a 2.5V or 3.3V
I/O version . Th e device is ideally suited for 486,
Pen tium ®, an d PowerPC system s an d th ose system s
th at ben efit from a wide syn ch ron ous data bus. Th e
device is also ideal in gen eric 16-, 18-, 32-, 36-, 64-, an d
72-bit-wide application s.
Micron ’s 4Mb Syn cBurst SRAMs in tegrate a 256K x
18, 128K x 32, or 128K x 36 SRAM core with advan ced
synchronousperipheralcircuitry and a 2-bit burst counter.
All syn ch ron ous in puts pass th rough registers con -
trolled by a positive-edge-triggered sin gle clock in put
(CLK). Th e syn ch ron ous in puts in clude all addresses, all
data in puts, active LOW ch ip en able (CE#), two addi-
tion al ch ip en ables for easy depth expan sion (CE2#,
CE2), burst con trol in puts (ADSC#, ADSP#, ADV#), byte
write en ables (BWx#) an d global write (GW#).
Asyn ch ron ous in puts in clude th e output en able
(OE#), clock (CLK) an d sn ooze en able (ZZ). Th ere is also
a burst m ode in put (MODE) th at selects between in ter-
leaved an d lin ear burst m odes. Th e data-out (Q), en -
abled by OE#, is also asyn ch ron ous. WRITE cycles can
be from on e to two bytes wide (x18) or from on e to four
bytes wide (x32/x36), as con trolled by th e write con trol
in puts.
Burst operation can be in itiated with eith er address
status processor (ADSP#) or address status con troller
(ADSC#) in puts. Subsequen t burst addresses can be
Please refer to Micron ’s Web site (www.m icron .com /
products/datash eets/syn cds.h tm l) for th e latest data
sh eet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
DQd
DQd
NC/DQPd*
MODE
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VDDQ
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
DQc
NC
NC
NC
DQa
NC
NC
SA
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
DQb
DQb
DQc
DQc
VSS
VDD
NC
VSS
VSS
VDD
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
VDDQ
VSS
SA
SA
SA
SA
SA
SA
VDDQ
VSS
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
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