Datasheet > MT57W512H36CF-3.3

MT57W512H36CF-3.3

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器
页数	文件大小	规格书
28页	404K
描述
DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MT57W512H36CF-3.3 数据手册

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第1页

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第3页

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第4页

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第5页

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第6页

浏览型号MT57W512H36CF-3.3的Datasheet PDF文件第7页

2 MEG X 8, 1 MEG X 18, 512K X 36

1.8V VDD, HSTL, DDR SIO SRAM

Depth expansion is accomplished with a single

device select (LD#), which is received at K rising edge.

All synchronous inputs pass through registers con-

trolled by the K or K# input clock rising edges. Active

LOW byte writes (BWx#) permit byte write or nibble

write selection. Write data and byte writes are regis-

tered on the rising edges of both K and K#. The

addressing within each burst of two is fixed and

sequential, beginning with the lowest address and

ending with the highest address. All synchronous data

outputs pass through output registers controlled by

the rising edges of the output clocks (C and C# if pro-

vided, otherwise K, K#).

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test

clock (TCK), and test data-out (TDO). JTAG circuitry is

used to serially shift data to and from the SRAM. JTAG

inputs use JEDEC-standard 1.8V I/O levels to shift data

during this testing mode of operation.

READ cycles are pipelined. The request is initiated

by driving R/W# HIGH and providing the address at K

rising edge. Data is delivered after the next rising edge

of K# (t + 1), using C and C# as the output timing refer-

ences; or K and K# if C and C# are tied HIGH. If C and

C# are tied HIGH, they may not be toggled during

device operation. Output tri-stating is automatically

controlled so that the bus is released if no data is being

delivered. This permits banked SRAM systems with no

complex output enable (OE) timing generation. Back-

to-back READ cycles can be initiated at every K rising

edge.

WRITE cycles are initiated by driving R/W# LOW

and providing the address at K rising edge. Data is

expected at the rising edge of K and K#, beginning at

the next K rising edge after the cycle is initiated. Write

registers are incorporated to facilitate pipelined self-

timed WRITE cycles and to provide fully coherent data

for all combinations of reads and writes. A read can

immediately follow a write even if they are to the same

address. Although the write data has not been written

to the memory array, the SRAM will deliver the data

from the write register instead of using the older data

from the memory array. The latest data is always uti-

lized for all bus transactions. WRITE cycles can be ini-

tiated on every K rising edge.

The SRAM operates from a 1.8V power supply, and

all inputs and outputs are HSTL-compatible. The

device is ideally suited for applications that require a

new transaction to be initiated each clock cycle.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

READ/WRITE Operations

All bus transactions operate on an uninterruptable

burst-of-two data and require one full clock cycle of

bus utilization. Any transaction type can be initiated at

K rising edge independent of the previous transaction

type. This permits any random operation without ever

needing bus turnaround delays.

PARTIAL WRITE Operations

BYTE WRITE operations are supported, except for

x8 devices in which nibble write is supported. The

active LOW byte write controls, BWx# (NWx#), are reg-

istered coincident with their corresponding data. This

feature can eliminate the need for some READ-MOD-

IFY-WRITE cycles, collapsing it to a single BYTE/NIB-

BLE WRITE operation in some instances.

18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V VDD, HSTL, DDR SIO SRAM

MT57W1MH18C_H.fm – Rev. H, Pub. 3/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

123 4 5 6 7...28

中文翻译

下载PDF

与MT57W512H36CF-3.3相关器件

型号	品牌	获取价格	描述	数据表
MT57W512H36CF-4	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36CF-5	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36CF-6	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36CF-7.5	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36JF-4	ROCHESTER	获取价格	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36JF-5	ROCHESTER	获取价格	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36JF-6	ROCHESTER	获取价格	512KX36 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W512H36JF-7.5	ROCHESTER	获取价格	512KX36 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT5850_IR	MARKTECH	获取价格	Peak Emission Wavelength: 850nm
MT5850-IR	MARKTECH	获取价格	Peak Emission Wavelength: 850nm

与MT57W512H36CF-3.3相关文章

LM317T数据手册解读：产品特性、应用、封装与引脚详解
2024-06-14

5
一文带你了解?DB3二极管好坏判断、参数信息、替代推荐
2024-06-14

10
LM358DR数据手册：引脚说明、电气参数及替换型号推荐
2024-06-14

4
OP07CP数据手册解读：引脚信息、电子参数
2024-06-14

4

产品中心

服务支持

精选活动

关于我们

帮助中心

MT57W512H36CF-3.3

MT57W512H36CF-3.3 数据手册

与MT57W512H36CF-3.3相关器件

与MT57W512H36CF-3.3相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MT57W512H36CF-3.3

MT57W512H36CF-3.3 数据手册

与MT57W512H36CF-3.3相关器件

与MT57W512H36CF-3.3相关文章

您还可以找

您在本页遇到什么问题？