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MSM7582B PDF预览

MSM7582B

更新时间: 2024-01-19 20:11:44
品牌 Logo 应用领域
冲电气 - OKI 调制解调器
页数 文件大小 规格书
24页 180K
描述
pie/4 Shift QPSK MODEM

MSM7582B 技术参数

生命周期:Obsolete零件包装代码:TSOP1
包装说明:TSOP1,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84数据速率:384 Mbps
JESD-30 代码:R-PDSO-G32长度:12.4 mm
功能数量:1端子数量:32
最高工作温度:70 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
标称供电电压:3 V表面贴装:YES
技术:CMOS电信集成电路类型:MODEM
温度等级:OTHER端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:8 mmBase Number Matches:1

MSM7582B 数据手册

 浏览型号MSM7582B的Datasheet PDF文件第4页浏览型号MSM7582B的Datasheet PDF文件第5页浏览型号MSM7582B的Datasheet PDF文件第6页浏览型号MSM7582B的Datasheet PDF文件第8页浏览型号MSM7582B的Datasheet PDF文件第9页浏览型号MSM7582B的Datasheet PDF文件第10页 
¡ Semiconductor  
MSM7582/7582B  
ENV  
I2 + Q2  
Quadrature modulation signal envelope (  
)output.  
Its output level is 500 mV with 1.6 Vdc as a center value. The output pin load conditions are  
PP  
: R 10 kW, C 20 pF. The gain of this output can be adjusted using the control register CR2 – B7  
to B4.  
This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of  
the demodulator block during the test mode. Refer to the description of the control register for  
details.  
SG  
Internal reference voltage output.  
The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and  
the AGND pin.  
PDN0, PDN1, PDN2  
Inputs for power-down control.  
PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2  
controls the demodulator. Refer to Table 1 for details.  
Table-1 Power Down Control  
PDN0 PDN2 PDN1  
Function  
Mode  
Mode A  
Mode B  
0
0
0/1  
0
1
0
All power-down. The control register is reset.  
All power-down. The control register is not reset.  
Modulator power is off (VREF and PLL power are also off).  
Demodulator power is on.  
Standby  
Mode  
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
Mode C  
Mode D  
Mode E  
Mode F  
Mode G  
Modulator power is off (VREF and PLL power is on).  
I and Q outputs are in a high-impedance state.  
Only demodulator clock recovery block power is on.  
Modulator power is on  
Only demodulator clock recovery block power is on.  
Modulator power is off (VREF and PLL power is on).  
I and Q outputs are in a high-impedance state.  
Demodulator power is on.  
Communication  
Mode  
Modulator power is on  
Demodulator power is on.  
V
DD  
+3 V power supply voltage.  
AGND  
Analog signal ground.  
DGND  
Digital signal ground.  
AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on  
the PCB as close as possible from the device.  
7/24  

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