MSM7566GS-K

更新时间： 2024-01-19 16:54:03

品牌	Logo	应用领域
冲电气 - OKI		解码器编解码器电信集成电路电信电路光电二极管 PC
页数	文件大小	规格书
19页	177K
描述
Single Rail CODEC

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技术参数
数据手册

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MSM7566GS-K 技术参数

生命周期：	Obsolete	零件包装代码：	TSOP
包装说明：	TSOP2,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
压伸定律：	MU-LAW	滤波器：	YES
JESD-30 代码：	R-PDSO-G20	长度：	17.14 mm
功能数量：	1	端子数量：	20
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-30 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	PCM CODEC	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.62 mm
Base Number Matches：	1

MSM7566GS-K 数据手册

¡ Semiconductor

MSM7566/7567

BCLOCK

Shift clock signal input for the PCMIN and PCMOUT signal.

WhenthefrequencyoftheSYNCpulseisat8kHz, theBCLOCKfrequency, equaltothedatarate,

is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 kHz. Setting this signal to logic

"1" or "0" drives both transmit and receive circuits to the power saving state.

RSYNC

Receive synchronizing signal input.

Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive

synchronizing signal.

Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee

the AC characteristics which are mainly the frequency characteristics of the receive section.

However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed. Even if the RSYNC signal is not present, the device is not in power saving state.

XSYNC

Transmit synchronizing signal input.

The PCM output signal from the PCMOUT pin is output in synchronization with this transmit

synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing

signals of the transmit section.

This synchronizing signal must be synchronized in phase with BCLOCK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.

However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving

state.

TMC

Control signal input for mode selection.

This pin select the normal operating mode or the analog loop-back mode.

In the analog loop-back mode, the receive filter output is connected to the transmit filter input

and the digital signal input to the PCMIN pin is converted from a digital to an analog signal (D/

A conversion). Next, the analog signal is converted to a digital signal (A/D conversion) through

the receive filter and transmit filter. The result is output to the PCMOUT pin.

When in the analog loop-back mode, the VFRO pin outputs the SG level. (signal ground)

TMC Input

< 0.16 ¥ V_DD

> 0.45 ¥ V_DD

Mode

Normal operation

Analog loop-back

6/19

1...3 4 567 8 9...19

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