Document Number: MPC8533EEC
Rev. 4, 09/2010
Freescale Semiconductor
Technical Data
MPC8533E PowerQUICC III
Integrated Processor
Hardware Specifications
Contents
1 MPC8533E Overview
This section provides a high-level overview of MPC8533E
features. Figure 1 shows the major functional units within
the device.
1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8. Enhanced Three-Speed Ethernet (eTSEC),
1.1
Key Features
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9. Ethernet Management Interface Electrical
The following list provides an overview of the device feature
set:
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
11. Programmable Interrupt Controller . . . . . . . . . . . . . .50
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . .58
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .76
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
21. System Design Information . . . . . . . . . . . . . . . . . . .100
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . .109
23. Document Revision History . . . . . . . . . . . . . . . . . . .111
•
High-performance, 32-bit core enhanced by
resources for embedded cores defined by the Power
ISA, and built on Power Architecture® technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
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