MM74HC137N

更新时间： 2024-01-27 23:49:49

品牌	Logo	应用领域
美国国家半导体 - NSC		解码器驱动器锁存器逻辑集成电路光电二极管
页数	文件大小	规格书
6页	125K
描述
3-to-8 Line Decoder With Address Latches (Inverted Output)

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技术参数
数据手册

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MM74HC137N 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP16,.3	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDIP-T16
JESD-609代码：	e0	逻辑集成电路类型：	OTHER DECODER/DRIVER
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	2/6 V
认证状态：	Not Qualified	子类别：	Decoder/Drivers
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL

MM74HC137N 数据手册

November 1995

MM54HC137/MM74HC137 3-to-8 Line

Decoder With Address Latches

(Inverted Output)

General Description

This device utilizes advanced silicon-gate CMOS technolo-

gy, to implement a three-to-eight line decoder with latches

on the three address inputs. When GL goes from low to

high, the address present at the select inputs (A, B and C) is

stored in the latches. As long as GL remains high no ad-

dress changes will be recognized. Output enable controls,

G1 and G2, control the state of the outputs independently of

the select or latch-enable inputs. All of the outputs are high

unless G1 is high and G2 is low. The HC137 is ideally suited

for the implementation of glitch-free decoders in stored-ad-

dress applications in bus oriented systems.

The 54HC/74HC logic family is speed, function and pin-out

compatible with the standard 54LS/74LS logic family. All

inputs are protected from damage due to static discharge by

diodes to V

and ground.

Features

Typical propagation delay: 20 ns

Wide supply range: 2–6V

Latched inputs for easy interfacing.

Fanout of 10 LS-TTL loads.

Connection and Functional Block Diagrams

Dual-In-Line Package

TL/F/5310–1

Order Number MM54HC137

or MM74HC137

TL/F/5310–2

1995 National Semiconductor Corporation

TL/F/5310

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6

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