5秒后页面跳转
MK2059-01SI PDF预览

MK2059-01SI

更新时间: 2024-01-18 09:53:30
品牌 Logo 应用领域
矽成 - ICSI 晶体转换器外围集成电路石英晶振压控振荡器光电二极管时钟
页数 文件大小 规格书
10页 145K
描述
VCXO-Based Frame Clock Frequency Translator

MK2059-01SI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.78
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm湿度敏感等级:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:25.92 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:27 MHz
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Clock Generators最大压摆率:15 mA
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK2059-01SI 数据手册

 浏览型号MK2059-01SI的Datasheet PDF文件第2页浏览型号MK2059-01SI的Datasheet PDF文件第3页浏览型号MK2059-01SI的Datasheet PDF文件第4页浏览型号MK2059-01SI的Datasheet PDF文件第5页浏览型号MK2059-01SI的Datasheet PDF文件第6页浏览型号MK2059-01SI的Datasheet PDF文件第7页 
MK2059-01  
VCXO-Based Frame Clock Frequency Translator  
Description  
Features  
The MK2059-01 is a VCXO (Voltage Controlled Crystal  
Oscillator) based clock generator that produces  
common telecommunications reference frequencies.  
The output clock is phase locked to an 8kHz (frame  
rate) input reference clock. The MK2059-01 also  
provides jitter attenuation. Included in the selection of  
output frequencies are these common system clocks:  
Generates T1, E1, OC-3 and other common telecom  
clock frequencies from an 8kHz frame clock  
Configurable jitter attenuation characterisitics,  
excellent for use as a Stratum source de-jitter circuit  
2:1 Input MUX for input reference clocks  
VCXO-based clock generation offers very low jitter  
and phase noise generation  
Output clock is phase and frequency locked to the  
1.544 MHz (T1)  
2.048 (E1)  
selected input reference clock  
19.44 MHz (OC-3)  
16.384 MHz (8x E1)  
Fixed input to output phase relationship  
This monolithic IC, combined with an external  
+115ppm minimum crystal frequency pullability  
range, using recommended crystal  
inexpensive quartz crystal, can be used to replace a  
more costly hybrid VCXO retiming module. Through  
selection of external loop filter components, the PLL  
loop bandwidth and damping factor can be tailored to  
meet input clock jitter attenuation requirements. A loop  
bandwidth down to the Hz range is possible.  
Industrial temperature range  
Low power CMOS technology  
20 pin SOIC package  
Single 3.3V power supply  
Block Diagram  
Pullable xtal  
VDD  
3
ISET  
X1  
X2  
VDD  
ICLK2  
1
0
8kHz Ref Input  
8kHz Ref Input  
Phase  
Output  
Divider  
CLK  
VCXO  
ICLK1  
Detector  
Charge  
Pump  
ISEL  
Feedback  
Divider  
3
SEL2:0  
CHGP  
VIN  
GND  
4
MDS 2059-01 B  
1
Revision 071001  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com  

与MK2059-01SI相关器件

型号 品牌 描述 获取价格 数据表
MK2059-01SITR ICSI VCXO-Based Frame Clock Frequency Translator

获取价格

MK2069-01 ICSI VCXO-Based Line Card Clock Synchronizer

获取价格

MK2069-01GI ICSI VCXO-Based Line Card Clock Synchronizer

获取价格

MK2069-01GITR ICSI VCXO-Based Line Card Clock Synchronizer

获取价格

MK2069-02GI IDT Clock Generator, 160MHz, CMOS, PDSO56, 6.10 MM, 0.50 MM PITCH, TSSOP-56

获取价格

MK2069-03 ICSI VCXO-Based Clock Translator with High Multiplication

获取价格