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MK2069-03GI PDF预览

MK2069-03GI

更新时间： 2024-11-25 03:49:15
品牌 Logo 应用领域
艾迪悌 - IDT 晶体转换器时钟发生器微控制器和处理器外围集成电路石英晶振压控振荡器光电二极管
页数 文件大小 规格书
21页 398K
描述
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION

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中文翻译

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MK2069-03GI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-56针数：56
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.91
Is Samacsys：NJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
湿度敏感等级：1端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：160 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3.3 V
主时钟/晶体标称频率：27 MHz认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大压摆率：30 mA最大供电电压：3.45 V
最小供电电压：3.15 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：6.1 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

MK2069-03GI 数据手册

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DATASHEET  
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03  
Description  
Features  
The MK2069-03 is a VCXO (Voltage Controlled Crystal  
Oscillator) based clock generator that offers system  
synchronization, jitter attenuation and frequency  
translation. It can accept an input clock over a wide range of  
frequencies and produces a de-jittered, low phase noise  
clock output. The device is optimized for user configuration  
by providing access to all major PLL divider functions. No  
power-up programming is needed as configuration is pin  
selected. External VCXO loop filter components provide an  
additional level of performance tailoring.  
• Wide range VCXO PLL feedback divider allows high  
frequency multiplication ratios and the input of very low  
input reference frequencies  
• Input clock frequency of <1kHz to 13.5MHz  
• Output clock frequency of 500kHz to 160MHz  
• PLL lock status output  
• VCXO-based clock generation offers very low jitter and  
phase noise generation, even with low frequency or jittery  
input clock.  
• PLL Clear function (CLR input) allows the VCXO to  
free-run, offering a short term holdover function.  
The MK2069-03 features a very wide range VCXO PLL  
feedback divider, allowing high frequency multiplication  
ratios and therefore the input of very low input reference  
frequencies. The lock detector (LD) output serves as a  
clock status monitor. The clear (CLR) input enables rapid  
synchronization to the phase of a newly selected input  
clock, while eliminating the generation of extra clock cycles  
and wander caused by memory in the PLL feedback divider.  
CLR also serves as a temporary holdover function when  
kept low.  
• 2nd PLL provides frequency translation of VCXO PLL to  
higher or alternate output frequencies.  
• Device will free-run in the absence of an input clock (or  
stopped input clock) based on the VCXO frequency  
pulled to minimum frequency limit.  
• Low power CMOS technology  
• 56 pin TSSOP package  
• Single 3.3V power supply  
Block Diagram  
Pullable  
xtal  
SV2:0  
RT1:0  
ST1:0  
VDD  
3
2
2
4
ISET  
LF  
LFR  
X1  
X2  
VCLK  
OEV  
Phase  
Detector  
SV  
RT  
ST  
Divider  
1,2,4,6,8,  
10,12,16  
ICLK  
VCXO  
VCO  
TCLK  
OET  
Divider  
1 to 4  
Divider  
2,4,8,16  
Charge  
Pump  
FV Divider  
1 to 4096  
FPV Divider  
2 to 65  
FT Divider  
1 to 64  
Translator  
PLL  
VCXO  
PLL  
RCLK  
Lock Detector  
OER  
LD  
CLR  
OEL  
12  
FV11:0  
6
6
4
LDC  
LDR  
FPV5:0  
FT5:0  
GND  
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1  
MK2069-03  
REV J 030906  
1234567...21

中文翻译

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