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MK2069-03

更新时间： 2024-11-25 03:49:15

品牌	Logo	应用领域
艾迪悌 - IDT		转换器石英晶振压控振荡器时钟
页数	文件大小	规格书
21页	398K
描述
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION

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中文翻译

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数据手册

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MK2069-03 数据手册

DATASHEET

VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03

Description

Features

The MK2069-03 is a VCXO (Voltage Controlled Crystal

Oscillator) based clock generator that offers system

synchronization, jitter attenuation and frequency

translation. It can accept an input clock over a wide range of

frequencies and produces a de-jittered, low phase noise

clock output. The device is optimized for user configuration

by providing access to all major PLL divider functions. No

power-up programming is needed as configuration is pin

selected. External VCXO loop filter components provide an

additional level of performance tailoring.

• Wide range VCXO PLL feedback divider allows high

frequency multiplication ratios and the input of very low

input reference frequencies

• Input clock frequency of <1kHz to 13.5MHz

• Output clock frequency of 500kHz to 160MHz

• PLL lock status output

• VCXO-based clock generation offers very low jitter and

phase noise generation, even with low frequency or jittery

input clock.

• PLL Clear function (CLR input) allows the VCXO to

free-run, offering a short term holdover function.

The MK2069-03 features a very wide range VCXO PLL

feedback divider, allowing high frequency multiplication

ratios and therefore the input of very low input reference

frequencies. The lock detector (LD) output serves as a

clock status monitor. The clear (CLR) input enables rapid

synchronization to the phase of a newly selected input

clock, while eliminating the generation of extra clock cycles

and wander caused by memory in the PLL feedback divider.

CLR also serves as a temporary holdover function when

kept low.

• 2nd PLL provides frequency translation of VCXO PLL to

higher or alternate output frequencies.

• Device will free-run in the absence of an input clock (or

stopped input clock) based on the VCXO frequency

pulled to minimum frequency limit.

• Low power CMOS technology

• 56 pin TSSOP package

• Single 3.3V power supply

Block Diagram

Pullable

xtal

SV2:0

RT1:0

ST1:0

VDD

ISET

LFR

VCLK

OEV

Phase

Detector

Divider

1,2,4,6,8,

10,12,16

ICLK

VCXO

VCO

TCLK

OET

Divider

1 to 4

Divider

2,4,8,16

Charge

Pump

FV Divider

1 to 4096

FPV Divider

2 to 65

FT Divider

1 to 64

Translator

PLL

VCXO

PLL

RCLK

Lock Detector

OER

CLR

OEL

FV11:0

LDC

LDR

FPV5:0

FT5:0

GND

IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1

MK2069-03

REV J 030906

12 3 4 5 6 7...21

中文翻译

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与MK2069-03相关器件

型号	品牌	获取价格	描述	数据表
MK2069-03GI	IDT	获取价格	VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
MK2069-03GI	ICSI	获取价格	VCXO-Based Clock Translator with High Multiplication
MK2069-03GILF	IDT	获取价格	Clock Generator, 160MHz, CMOS, PDSO56, 6.10 MM, 0.50 MM PITCH, TSSOP-56
MK2069-03GILFTR	IDT	获取价格	暂无描述
MK2069-03GITR	ICSI	获取价格	VCXO-Based Clock Translator with High Multiplication
MK2069-03GITR	IDT	获取价格	VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
MK2069-04	ICSI	获取价格	VCXO-Based Universal Clock Translator
MK2069-04GI	ICSI	获取价格	VCXO-Based Universal Clock Translator
MK2069-04GITR	ICSI	获取价格	VCXO-Based Universal Clock Translator
MK20-B-100W	MEDER	获取价格	MK Reed Sensor

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