Datasheet > MH32D72KLH-10

MH32D72KLH-10

更新时间： 2024-01-16 13:48:21

品牌	Logo	应用领域
三菱 - MITSUBISHI		动态存储器
页数	文件大小	规格书
39页	341K
描述
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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MH32D72KLH-10 数据手册

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32D72KLH-75,-10

2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

DESCRIPTION

The MH32D72KLH is 33554432 - word x 72-bit Double

Data Rate(DDR) Sy nchronous DRAM mounted module.

This consists of 9 industry standard 32M x 8 DDR

Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which

achiev es v ery high speed data rate up to 133MHz.

This socket-ty pe memory module is suitable f or main

memory in computer systems and easy to interchange or

add modules.

93pin

1pin

FEATURES

CLK

Max.

Access Time

[component level]

Type name

Frequency

+ 0.75ns

MH32D72KLH-75

MH32D72KLH-10

133MHz

100MHz

+ 0.8ns

144pin

145pin

- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs

in TSOP package , industry standard Registered Buffer in

TSSOP package , and industry standard PLL in TSSOP package.

- Vdd=Vddq=2.5v ±0.2V

52pin

53pin

- Double data rate architecture; two data transf ers per

clock cycle

- Bidirectional, data strobe (DQS) is transmitted/receiv ed

with data

- Dif f erential clock inputs (CK0 and /CK0)

- data and data mask ref erenced to both edges of DQS

- /CAS latency - 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Auto precharge / All bank precharge controlled by A10

- 8192 ref resh cycles /64ms

- Auto ref resh and Self ref resh

- Row address A0-12 / Column address A0-9

- SSTL_2 Interf ace

184pin

92pin

- Module 1bank Conf igration

- Burst Ty pe - sequential/interleav e(programmable)

- Commands entered on each positiv e CLK edge

APPLICATION

Main memory unit for PC, PC server, Server, W S.

MIT-DS-0391-1.0

24.Nov.2000

MITSUBISHI ELECTRIC

12 3 4 5 6 7...39

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