MCP23016
input or output register. The polarity of the read register
can be inverted with the polarity inversion register (see
Section 1.7.3, “Input Polarity Registers”). All
registers can be read by the system master.
1.0
DEVICE OVERVIEW
The MCP23016 device provides 16-bit, general
purpose, parallel I/O expansion for I2C bus
applications.
The open-drain interrupt output is activated when any
input state differs from its corresponding input port
register state. This is used to indicate to the system
master that an input state has changed. The interrupt
capture register captures port value at this time. The
Power-on Reset sets the registers to their default val-
ues and initializes the device state machine.
Three device inputs (A0 - A2) determine the I2C
address and allow up to eight I/O expander devices to
share the same I2C bus.
This device includes high-current drive capability, low
supply current and individual I/O configuration. I/O
expanders provide a simple solution when additional
I/Os are needed for ACPI, power switches, sensors,
push buttons, LEDs and so on.
The MCP23016 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
1.1
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTION
PDIP,
SOIC,
SSOP
QFN
Pin No.
I/O/P
Type
Buffer
Pin Name
Description
Type
Pin No.
CLK
9
10
2
6
7
I
ST
—
Clock source input
TP
O
Test Pin (This pin must be left floating)
D0 digital input/output for GP1
D1 digital input/output for GP1
D2 digital input/output for GP1
D3 digital input/output for GP1
D4 digital input/output for GP1
D5 digital input/output for GP1
D6 digital input/output for GP1
D7 digital input/output for GP1
D0 digital input/output for GP0
D1 digital input/output for GP0
D2 digital input/output for GP0
D3 digital input/output for GP0
D4 digital input/output for GP0
D5 digital input/output for GP0
D6 digital input/output for GP0
D7 digital input/output for GP0
Serial clock input
GP1.0
GP1.1
GP1.2
GP1.3
GP1.4
GP1.5
GP1.6
GP1.7
GP0.0
GP0.1
GP0.2
GP0.3
GP0.4
GP0.5
GP0.6
GP0.7
SCL
27
28
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
ST
3
4
5
2
7
4
11
12
13
21
22
23
24
25
26
27
28
14
15
6
8
9
ST
10
18
19
20
21
22
23
24
25
11
12
3
ST
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
SDA
I/O
O
ST
Serial data I/O
INT
OD
ST
Interrupt output
A0
16
17
18
1, 8, 19
20
13
14
15
5, 16, 26
17
I
Address input 1
A1
I
ST
Address input 2
A2
I
ST
Address input 3
VSS
P
—
Ground reference for logic and I/O pins
Positive supply for logic and I/O pins
VDD
P
—
© 2007 Microchip Technology Inc.
DS20090C-page 3