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MC74AC161DW PDF预览

MC74AC161DW

更新时间: 2024-02-19 00:36:58
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
12页 312K
描述
AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOIC-16

MC74AC161DW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.19
计数方向:UP系列:AC
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:60000000 Hz最大I(ol):0.012 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3/5 V传播延迟(tpd):13.5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:95 MHzBase Number Matches:1

MC74AC161DW 数据手册

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SYNCHRONOUS  
PRESETTABLE  
BINARY COUNTER  
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed  
synchronous modulo-16 binary counters. They are synchronously presettable for  
application in programmable dividers and have two types of Count Enable inputs  
plus a Terminal Count output for versatility in forming synchronous multistage  
counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input  
that overrides all other inputs and forces the outputs LOW. The MC74AC163/  
74ACT163 has a Synchronous Reset input that overrides counting and parallel  
loading and allows the outputs to be simultaneously reset on the rising edge of  
the clock.  
N SUFFIX  
CASE 648-08  
PLASTIC  
Synchronous Counting and Loading  
High-Speed Synchronous Expansion  
Typical Count Rate of 125 MHz  
Outputs Source/Sink 24 mA  
• ′ACT161 and ACT163 Have TTL Compatible Inputs  
V
TC  
15  
Q
Q
Q
Q
3
CET  
10  
PE  
9
CC  
0
1
2
16  
14  
13  
12  
11  
D SUFFIX  
CASE 751B-05  
PLASTIC  
LOGIC SYMBOL  
1
2
3
4
5
6
7
8
*R  
CP  
P
P
P
P
3
CEP GND  
0
1
2
PE P  
CEP  
P
P
P
0
1
2 3  
PIN NAMES  
CET  
CP  
*R Q  
TC  
CEP  
CET  
CP  
Count Enable Parallel Input  
Count Enable Trickle Input  
Clock Pulse Input  
Q Q Q  
1 2 3  
0
MR  
SR  
(161) Asynchronous Master Reset Input  
(163) Synchronous Reset Input  
Parallel Data Inputs  
P –P  
0
3
*MR for  
*SR for  
161  
PE  
Parallel Enable Input  
163  
Q –Q  
TC  
Flip-Flop Outputs  
Terminal Count Output  
0
3
FACT DATA  
5-1  

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