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MC7447AHX1000LB PDF预览

MC7447AHX1000LB

更新时间: 2024-02-26 11:31:58
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
56页 1025K
描述
APOLO7PM,RV1.1,1.3V,105C

MC7447AHX1000LB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:BGA
包装说明:25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360针数:360
Reach Compliance Code:not_compliantECCN代码:3A991.A.1
HTS代码:8542.31.00.01风险等级:5.26
其他特性:ALSO REQUIRES 1.8V OR 2.5V SUPPLY地址总线宽度:36
位大小:32边界扫描:YES
最大时钟频率:167 MHz外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-CBGA-B360JESD-609代码:e0
长度:25 mm低功率模式:YES
湿度敏感等级:1端子数量:360
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装等效代码:BGA360,19X19,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.3,1.8/2.5 V认证状态:Not Qualified
座面最大高度:3.24 mm速度:1000 MHz
子类别:Microprocessors最大供电电压:1.35 V
最小供电电压:1.25 V标称供电电压:1.3 V
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:25 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

MC7447AHX1000LB 数据手册

 浏览型号MC7447AHX1000LB的Datasheet PDF文件第3页浏览型号MC7447AHX1000LB的Datasheet PDF文件第4页浏览型号MC7447AHX1000LB的Datasheet PDF文件第5页浏览型号MC7447AHX1000LB的Datasheet PDF文件第7页浏览型号MC7447AHX1000LB的Datasheet PDF文件第8页浏览型号MC7447AHX1000LB的Datasheet PDF文件第9页 
Features  
– TLBs are hardware- or software-reloadable (that is, a page table search is performed in  
hardware or by system software on a TLB miss).  
Efficient data flow  
— Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.  
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.  
— The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache.  
— As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache  
and the L2 bus.  
— As many as 16 out-of-order transactions can be present on the MPX bus.  
— Store merging for multiple store misses to the same line. Only coherency action taken  
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).  
— Three-entry finished store queue and five-entry completed store queue between the LSU and  
the L1 data cache  
— Separate additional queues for efficient buffering of outbound data (such as castouts and  
write-through stores) from the L1 data cache and L2 cache  
Multiprocessing support features include the following:  
— Hardware-enforced, MESI cache coherency protocols for data cache  
— Load/store with reservation instruction pair for atomic memory references, semaphores, and  
other multiprocessor operations  
Power and thermal management  
— A new dynamic frequency switching (DFS) feature allows processor core frequency to be  
halved through software to reduce power consumption.  
— The following three power-saving modes are available to the system:  
– Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and  
JTAG logic remain running. The part goes into the doze state to snoop memory operations  
on the bus and then back to nap using a QREQ/QACK processor-system handshake  
protocol.  
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the  
PLL in a locked and running state. All internal functional units are disabled.  
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system  
can then disable the SYSCLK source for greater system power savings. Power-on reset  
procedures for restarting and relocking the PLL must be followed upon exiting the deep  
sleep state.  
— Instruction cache throttling provides control of instruction fetching to limit device temperature.  
— A new temperature diode can determine the temperature of the microprocessor.  
— Support for core voltage derating to further reduce power consumption  
Performance monitor can be used to help debug system designs and improve software efficiency.  
In-system testability and debugging features through JTAG boundary-scan capability  
Testability  
— LSSD scan design  
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5  
6
Freescale Semiconductor  

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