Datasheet > MC33742PEGR2

MC33742PEGR2

更新时间： 2024-01-16 01:15:19

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
72页	1211K
描述
System Basis Chip, CAN, 2x 5.0V/200mA LDOs, 4 wake ups, 15 ms reset duration, SOIC 28, Reel

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技术参数
数据手册

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MC33742PEGR2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	Reach Compliance Code：	unknown
风险等级：	2.12	Base Number Matches：	1

MC33742PEGR2 数据手册

INTERNAL BLOCK DIAGRAM

V2CTRL

VSUP Monitor

Dual Voltage Regulator

VSUP

5.0V/200mA

V1 Monitor

HS Control

Mode Control

Oscillator

INT

Interrupt

Watchdog

Reset

WDOG

RST

MOSI

SCLK

MISO

Programmable

Wake-up Input

SPI

High-speed

1.0 Mbps

CAN Physical

Interface

CANH

CANL

TXD

RXD

GND

Figure 2. 33742 Simplified Internal Block Diagram

33742

Analog Integrated Circuit Device Data

Freescale Semiconductor

1 234 5 6 7...72

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