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MC10EL51D PDF预览

MC10EL51D

更新时间: 2024-01-07 05:40:36
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
20页 203K
描述
Evaluation Board Manual for High Frequency SOIC 8

MC10EL51D 技术参数

是否无铅: 不含铅生命周期:End Of Life
零件包装代码:SOIC包装说明:TSSOP, TSSOP8,.19
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.92Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V系列:10EL
JESD-30 代码:S-PDSO-G8JESD-609代码:e3
长度:3 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:2200000000 Hz湿度敏感等级:3
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:-5.2 V
最大电源电流(ICC):29 mAProp。Delay @ Nom-Sup:0.62 ns
传播延迟(tpd):0.565 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):4.2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:3 mm最小 fmax:2200 MHz
Base Number Matches:1

MC10EL51D 数据手册

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ECLSOIC8EVB  
Evaluation Board Manual  
for High Frequency SOIC 8  
http://onsemi.com  
EVALUATION BOARD MANUAL  
Board Lay−Up  
INTRODUCTION  
The 8−lead SOIC evaluation board is implemented in four  
layers with split (dual) power supplies (Figure 2.  
Evaluation Board Lay−up). For standard ECL lab setup and  
test, a split (dual) power supply is essential to enable the  
50 W internal impedance in the oscilloscope as a termination  
for ECL devices. The first layer or primary trace layer is  
0.008thick Rogers RO4003 material, which is designed to  
have equal electrical length on all signal traces from the  
device under the test (DUT) to the sense output. The second  
layer is the 1.0 oz copper ground plane and a portion of the  
ON Semiconductor has developed an evaluation board for  
the devices in 8−lead SOIC package. These evaluation  
boards are offered as a convenience for the customers  
interested in performing their own engineering assessment  
on the general performance of the 8−lead SOIC device  
samples. The board provides a high bandwidth 50 W  
controlled impedance environment. The pictures in Figure 1  
show the top and bottom view of the evaluation board, which  
can be configured in several different ways, depending on  
device under test (See Table 1. Configuration List).  
This evaluation board manual contains:  
plane is the V power plane. The FR4 dielectric material is  
EE  
placed between second and third layer and between third and  
fourth layer. The third layer is also 1.0 oz copper ground  
Information on 8−lead SOIC Evaluation Board  
Assembly Instructions  
Appropriate Lab Setup  
plane and a portion of this layer is V power plane. The  
CC  
fourth layer is the secondary trace layer.  
Bill of Materials  
This manual should be used in conjunction with the device  
data sheet, which contains full technical details on the device  
specifications and operation.  
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
August, 2004 − Rev. 1  
ECLSOIC8EVB/D  
 

MC10EL51D 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP52DG ONSEMI

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