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MC100EL59 PDF预览

MC100EL59

更新时间: 2024-02-17 12:23:30
品牌 Logo 应用领域
安森美 - ONSEMI 复用器
页数 文件大小 规格书
3页 102K
描述
Triple 2:1 Multiplexer

MC100EL59 技术参数

是否无铅:含铅生命周期:Active
零件包装代码:SOIC包装说明:LEAD FREE, SOIC-20
针数:20Reach Compliance Code:unknown
风险等级:5.73Is Samacsys:N
其他特性:NECL MODE OPERATING RANGE: VEE = -4.2 V TO -5.7 V WITH VCC = 0 V系列:100EL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:NOT SPECIFIED功能数量:3
输入次数:2输出次数:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):0.69 ns认证状态:COMMERCIAL
座面最大高度:2.65 mm最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

MC100EL59 数据手册

 浏览型号MC100EL59的Datasheet PDF文件第2页浏览型号MC100EL59的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC100LVEL59 is a triple 2:1 multiplexer with differential outputs.  
The MC100EL59 is pin and functionally equivalent to the MC100LVEL59  
but is specified for operation at the standard 100E ECL voltage supply.  
The output data of the muxes can be controlled individually via the select  
inputs or as a group via the common select input. The flexibile selection  
scheme makes the device useful for both data path and random logic  
applications.  
Individual or Common Select Controls  
20–Lead SOIC Packaging  
20  
1
500ps Typical Propagation Delays  
Supports Both Standard and Low Voltage 100K ECL  
Internal Input Pulldown Resistors  
>2000V ESD Protection  
DW SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751D–04  
Logic Diagram and Pinout: 20–Lead SOIC (Top View)  
V
Q0  
19  
Q0  
18  
V
Q1  
16  
Q1  
15  
V
Q2  
13  
Q2  
12  
V
CC  
CC  
CC  
EE  
TRUTH TABLE  
20  
17  
14  
11  
SEL  
Data  
H
L
a
b
1
0
1
0
1
0
PIN NAMES  
Pins  
Function  
1
2
3
4
5
6
7
8
9
10  
D0a–D1a  
D0b–D1b  
SEL0–SEL1  
COM_SEL  
Q0–Q2  
Input Data a  
Input Data b  
Individual Select Input  
Common Select Input  
True Outputs  
COM_SEL D0a  
D0b SEL0 D1a  
D1b SEL1 D2a  
D2b SEL2  
Q0–Q2  
Inverted Outputs  
4/95  
Motorola, Inc. 1996  
REV 1  

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