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MB9BF118TBGL-GK7E1 PDF预览

MB9BF118TBGL-GK7E1

更新时间: 2024-02-15 02:53:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器外围集成电路
页数 文件大小 规格书
133页 3827K
描述
32-bit ARM® Cortex®-M3 FM3 Microcontroller

MB9BF118TBGL-GK7E1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:,
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.82峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC

MB9BF118TBGL-GK7E1 数据手册

 浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第1页浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第2页浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第3页浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第5页浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第6页浏览型号MB9BF118TBGL-GK7E1的Datasheet PDF文件第7页 
MB9B110T Series  
Voltage Detector generates an interrupt or reset.  
Watchdog Timer (2 channels)  
A watchdog timer can generate interrupts or a reset when a  
time-out value is reached.  
LVD1: error reporting via interrupt  
LVD2: auto-reset operation  
This series consists of two different watchdogs, a "Hardware"  
watchdog and a "Software" watchdog.  
Low-Power Consumption Mode  
Three Low-Power Consumption modes supported.  
The "Hardware" watchdog timer is operated by the built-in  
low-speed CR oscillator. Therefore, the "Hardware" watchdog  
is active in any low-power consumption mode except STOP  
mode.  
Sleep  
Timer  
Stop  
Debug  
CRC (Cyclic Redundancy Check) Accelerator  
The CRC accelerator calculates the CRC which has a heavy  
software processing load, and achieves a reduction of the  
integrity check processing load for reception data and storage.  
Serial Wire JTAG Debug Port (SWJ-DP)  
Embedded Trace Macrocells (ETM).  
Power Supply  
CCITT CRC16 and IEEE-802.3 CRC32 are supported.  
Wide range voltage VCC = 2.7 V to 5.5 V  
CCITT CRC16 Generator Polynomial: 0x1021  
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  
Clock and Reset  
[Clocks]  
Selectable from five clock sources (2 external oscillators, 2  
built-in CR oscillators, and Main PLL).  
Main Clock: 4 MHz to 48 MHz  
Sub Clock: 32.768 kHz  
Built-in high-speed CR Clock: 4 MHz  
Built-in low-speed CR Clock: 100 kHz  
Main PLL Clock  
[Resets]  
Reset requests from INITX pin  
Power-on reset  
Software reset  
Watchdog timers reset  
Low-voltage detection reset  
Clock supervisor reset  
Clock Super Visor (CSV)  
Clocks generated by built-in CR oscillators are used to  
supervise abnormality of the external clocks.  
When external clock failure (clock stop) is detected, reset is  
asserted.  
When external frequency anomaly is detected, interrupt or  
reset is asserted.  
Low-Voltage Detector (LVD)  
This Series includes 2-stage monitoring of voltage on the VCC  
pins. When the voltage falls below the voltage set, Low  
Document Number: 002-04683 Rev.*C  
Page 3 of 132  

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