S in g le /Du a l, +3 V/+5 V Du a l-S p e e d
Co m p a ra t o rs w it h Au t o -S t a n d b y
5/MAX97
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +5.25V, specifications are for high-speed mode, T = -40°C to +85°C, unless otherwise noted. Typical values are at
CC
A
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
LP Input Voltage High
LP Input Voltage Low
LP Fall Time
V
0.7 xV
V / 2
CC
V
V
LPIH
CC
V
LPIL
V
/ 2 0.3 x V
CC CC
t
(Note 5)
10
µs
µA
V
LP
LP Input Current
I
0.01
±1
LPB
STO_ Input Voltage Low
STO_ Source Current
DIGITAL OUTPUTS
OUT_ Output Voltage High
OUT_ Output Voltage Low
V
V
/ 2 0.3 x V
CIL
CC CC
I
V
CC
= 3V
0.15
µA
STO
V
I
= 2mA, all modes
= 2mA, all modes
SINK
V
- 0.4
V - 0.1
CC
V
V
OH
CC
SOURCE
V
I
0.1
0.4
50
OL
High-speed mode,
overdrive = 5mV
28
0.82
28
ns
µs
ns
µs
Propagation Delay, Low to High
(Note 6)
C
= 10pF,
LOAD
t
PD+
V
CC
= 5V
Low-power mode,
overdrive = 10mV
1.6
50
High-speed mode,
overdrive = 5mV
Propagation Delay, High to Low
(Note 6)
C
V
CC
= 10pF,
= 10pF
LOAD
t
PD-
= 5V
Low-power mode,
overdrive = 10mV
0.48
1.6
Propagation-Delay Skew (Note 6)
Propagation-Delay Matching
t
C
2
1
ns
ns
SKEW
LOAD
∆t
MAX977 only, C
= 10pF
PD
LOAD
High-speed mode
Low-power mode
1.6
1.6
C
V
CC
= 10pF,
= 5.0V
LOAD
Rise/Fall Time
ns
STAT_ Output Voltage High
STAT_ Output Voltage Low
V
I
= 3mA, all modes
V
CC
- 0.4
V
V
SH
SOURCE
V
SL
I
= 400µA, all modes
0.4
SINK
Note 1: The MAX975EUA is 100% production tested at T = +25°C; all temperature specifications are guaranteed by design.
A
Note 2: Inferred by CMRR. Either input can be driven to the absolute maximum limit without false output inversion, as long as the
other input is within the specified common-mode input voltage range.
Note 3: V is defined as the mean of trip points. The trip points are the extremities of the differential input voltage required to make
OS
the comparator output change state (Figure 1).
Note 4: The difference between the upper and lower trip points is equal to the width of the input-referred hysteresis zone (Figure 1).
Note 5: Guaranteed by design. The LP pin is sensitive to noise. If fall times larger than 10µs are expected, bypass LP to ground
using a 0.1µF capacitor.
Note 6: Propagation delay is guaranteed by design. For low-overdrive conditions, V is added to the overdrive. The following
OS
equation defines propagation-delay skew: t
= t
- t
SKEW
PD+ PD-.
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