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MAX7324ATG+T PDF预览

MAX7324ATG+T

更新时间: 2024-01-31 01:22:38
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
20页 262K
描述
Parallel I/O Port, 16 I/O, BICMOS, TQFN-24

MAX7324ATG+T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC24,.16SQ,20针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.62
JESD-30 代码:S-XQCC-N24JESD-609代码:e0
长度:4 mmI/O 线路数量:
端口数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5 V认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Parallel IO Port
最大供电电压:5.5 V最小供电电压:1.71 V
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

MAX7324ATG+T 数据手册

 浏览型号MAX7324ATG+T的Datasheet PDF文件第4页浏览型号MAX7324ATG+T的Datasheet PDF文件第5页浏览型号MAX7324ATG+T的Datasheet PDF文件第6页浏览型号MAX7324ATG+T的Datasheet PDF文件第8页浏览型号MAX7324ATG+T的Datasheet PDF文件第9页浏览型号MAX7324ATG+T的Datasheet PDF文件第10页 
2
I C Port Expander with Eight Push-Pull Outputs  
and Eight Inputs  
Table 1. MAX7319–MAX7329 Family Comparison (continued)  
2
I C  
INPUT  
INPUTS INTERRUPT  
MASK  
OPEN-  
DRAIN  
OUTPUTS OUTPUTS  
PUSH-  
PULL  
PART  
SLAVE  
ADDRESS  
CONFIGURATION  
4 I/O, 4 output-only versions:  
4 open-drain I/O ports with latching transition  
detection interrupt and selectable pullups.  
4 push-pull outputs with selectable power-up default  
levels.  
MAX7323  
110xxxx  
Up to 4  
Up to 8  
Up to 4  
Up to 8  
4
PCF8574-, PCF8574A-compatible versions:  
8 open-drain I/O ports with nonlatching transition  
detection interrupt and pullups on all ports.  
MAX7328  
MAX7329  
0100xxx  
0111xxx  
A latching interrupt output, INT, is programmed to flag  
input data changes on input ports through an interrupt  
mask register. By default, data changes on any input  
port force INT to a logic-low. The interrupt output INT  
and all transition flags are cleared when the MAX7324  
is next accessed through the serial interface.  
RST Input  
2
The RST input voids any I C transaction involving the  
2
MAX7324, forcing the MAX7324 into the I C STOP con-  
dition. A reset does not affect the interrupt output (INT).  
Standby Mode  
When the serial interface is idle, the MAX7324 automat-  
ically enters standby mode, drawing minimal supply  
current.  
Internal pullup resistors to V+ are selected by the  
address select inputs, AD0 and AD2. Pullups are  
enabled on the input ports in groups of four (see Table 2).  
Slave Address, Power-Up Default Logic  
Levels, and Input Pullup Selection  
Address inputs AD0 and AD2 determine the MAX7324  
slave address and select which inputs have pullup  
resistors. Pullups are enabled on the input ports in  
groups of four (see Table 2).  
Initial Power-Up  
On power-up, the transition detection logic is reset, and  
INT is deasserted. The interrupt mask register is set to  
0xFF, enabling the interrupt output for transitions on all  
eight input ports. The transition flags are cleared to  
indicate no data changes. The power-up default states  
of the eight push-pull outputs are set according to the  
2
The MAX7324 slave address is determined on each I C  
2
transmission, regardless of whether the transmission is  
actually addressing the MAX7324. The MAX7324 distin-  
guishes whether address inputs AD0 and AD2 are con-  
nected to SDA or SCL instead of fixed logic levels V+  
or GND during this transmission. This means that the  
MAX7324 slave address can be configured dynamical-  
ly in the application without cycling the device supply.  
I C slave address selection inputs, AD0 and AD1 (see  
Table 3).  
Power-On Reset  
The MAX7324 contains an integral power-on-reset  
(POR) circuit that ensures all registers are reset to a  
known state on power-up. When V+ rises above V  
POR  
(1.6V max), the POR circuit releases the registers and  
2-wire interface for normal operation. When V+ drops  
On initial power-up, the MAX7324 cannot decode the  
2
address inputs AD0 and AD2 fully until the first I C  
below V  
, the MAX7324 resets all register contents  
POR  
transmission. AD0 and AD2 initially appear to be con-  
nected to V+ or GND. This is important because the  
to the POR defaults (Tables 2 and 3).  
_______________________________________________________________________________________  
7

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