Datasheet > MAX7324AEG+T

MAX7324AEG+T

更新时间： 2024-02-21 13:07:00

品牌	Logo	应用领域
美信 - MAXIM		信息通信管理光电二极管外围集成电路
页数	文件大小	规格书
18页	819K
描述
Parallel I/O Port, 0 I/O, BICMOS, PDSO24, 0.150 INCH, 0.25 INCH PITCH, ROHS COMPLIANT, MO-137AE, QSOP-24

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MAX7324AEG+T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP, SSOP24,.24	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.36
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e3
长度：	8.65 mm	湿度敏感等级：	1
I/O 线路数量：		端口数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP24,.24
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2/5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Parallel IO Port	最大供电电压：	5.5 V
最小供电电压：	1.71 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	AUTOMOTIVE	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：	1

MAX7324AEG+T 数据手册

MAX7324

I C Port Expander with

Eight Push-Pull Outputs and Eight Inputs

Table 1. MAX7319–MAX7329 Family Comparison (continued)

I C

INPUT

INPUTS INTERRUPT

MASK

OPEN-

PUSH-

PART

SLAVE

DRAIN

PULL

CONFIGURATION

ADDRESS

OUTPUTS OUTPUTS

4 I/O, 4 output-only versions:

4 open-drain I/O ports with latching transition

detection interrupt and selectable pullups.

MAX7323

110xxxx

Up to 4

Up to 8

—

Up to 4

Up to 8

4 push-pull outputs with selectable power-up default

levels.

PCF8574-, PCF8574A-compatible versions:

8 open-drain I/O ports with nonlatching transition

detection interrupt and pullups on all ports.

0100xxx

0111xxx

MAX7328

MAX7329

—

A latching interrupt output, INT, is programmed to flag

input data changes on input ports through an interrupt

mask register. By default, data changes on any input port

force INT to a logic-low. The interrupt output INT and all

transition flags are cleared when the MAX7324 is next

accessed through the serial interface.

Standby Mode

When the serial interface is idle, the MAX7324

automatically enters standby mode, drawing minimal

supply current.

Slave Address, Power-Up Default Logic

Levels, and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7324

slave address and select which inputs have pullup

resistors. Pullups are enabled on the input ports in groups

of four (see Table 2).

Internal pullup resistors to V+ are selected by the address

select inputs, AD0 and AD2. Pullups are enabled on the

input ports in groups of four (see Table 2).

Initial Power-Up

On power-up, the transition detection logic is reset, and

INT is deasserted. The interrupt mask register is set

to 0xFF, enabling the interrupt output for transitions on

all eight input ports. The transition flags are cleared to

indicate no data changes. The power-up default states of

The MAX7324 slave address is determined on each I C

transmission, regardless of whether the transmission

is actually addressing the MAX7324. The MAX7324

distinguishes whether address inputs AD0 and AD2 are

connected to SDA or SCL instead of fixed logic levels

V+ or GND during this transmission. This means that the

MAX7324 slave address can be configured dynamically in

the application without cycling the device supply.

the eight push-pull outputs are set according to the I C

slave address selection inputs, AD0 and AD1 (see Table 3).

Power-On Reset

The MAX7324 contains an integral power-on-reset

(POR) circuit that ensures all registers are reset to a

On initial power-up, the MAX7324 cannot decode

the address inputs AD0 and AD2 fully until the first

I C transmission. AD0 and AD2 initially appear to be

connected to V+ or GND. This is important because the

address selection determines which inputs have pullups

applied. However, at power-up, the I C SDA and SCL bus

known state on power-up. When V+ rises above V

POR

(1.6V max), the POR circuit releases the registers and

2-wire interface for normal operation. When V+ drops

below V

, the MAX7324 resets all register contents

POR

interface lines are high impedance at the inputs of every

device (master or slave) connected to the bus, includ-

to the POR defaults (Tables 2 and 3).

RST Input

ing the MAX7324. This is guaranteed as part of the I C

specification. Therefore, address inputs AD0 and AD2 that

are connected to SDA or SCL during power-up appear to

be connected to V+. The pullup selection logic uses AD0

to select whether pullups are enabled for ports I0–I3,

The RST input voids any I C transaction involving the

MAX7324, forcing the MAX7324 into the I C STOP

condition. A reset does not affect the interrupt output

(INT).

Maxim Integrated

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www.maximintegrated.com

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与MAX7324AEG+T相关器件

型号	品牌	描述	获取价格	数据表
MAX7324AEG-T	MAXIM	暂无描述	获取价格
MAX7324ATG	MAXIM	I2C Port Expander with Eight Push-Pull Outputs and Eight Inputs	获取价格
MAX7324ATG+	MAXIM	Parallel I/O Port, 0 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WGGD-2, TQFN-	获取价格
MAX7324ATG+T	MAXIM	Parallel I/O Port, 16 I/O, BICMOS, TQFN-24	获取价格
MAX7324ATG-T	MAXIM	Parallel I/O Port, 0 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD-2, TQFN-24	获取价格
MAX7325	MAXIM	I2C Port Expander with Eight Push-Pull Outputs and Eight Inputs	获取价格

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