5秒后页面跳转
MAX7324AEG PDF预览

MAX7324AEG

更新时间: 2024-02-25 13:40:32
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
20页 262K
描述
I2C Port Expander with Eight Push-Pull Outputs and Eight Inputs

MAX7324AEG 数据手册

 浏览型号MAX7324AEG的Datasheet PDF文件第1页浏览型号MAX7324AEG的Datasheet PDF文件第2页浏览型号MAX7324AEG的Datasheet PDF文件第4页浏览型号MAX7324AEG的Datasheet PDF文件第5页浏览型号MAX7324AEG的Datasheet PDF文件第6页浏览型号MAX7324AEG的Datasheet PDF文件第7页 
2
I C Port Expander with Eight Push-Pull Outputs  
and Eight Inputs  
PORT AND INTERRUPT INT TIMING CHARACTERISTICS  
(V+ = +1.71V to +5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T = +25°C.) (Note 1)  
A
A
PARAMETER  
Port-Output Data Valid  
Port-Input Setup Time  
Port-Input Hold Time  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
µs  
t
C
C
C
C
C
100pF  
100pF  
100pF  
100pF  
100pF  
4
PPV  
PSU  
L
L
L
L
L
t
0
4
µs  
t
µs  
PH  
INT Input Data Valid Time  
t
4
4
µs  
IV  
IP  
INT Reset Delay Time from STOP  
t
µs  
INT Reset Delay Time from  
Acknowledge  
t
IR  
C
100pF  
4
µs  
L
TIMING CHARACTERISTICS  
(V+ = +1.71V to +5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T = +25°C.) (Note 1)  
A
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Serial-Clock Frequency  
f
400  
kHz  
SCL  
Bus Free Time Between a STOP  
and a START Condition  
t
1.3  
0.6  
µs  
µs  
µs  
BUF  
Hold Time (Repeated) START  
Condition  
t
HD,STA  
Repeated START Condition  
Setup Time  
t
0.6  
0.6  
SU,STA  
STOP Condition Setup Time  
Data Hold Time  
t
µs  
µs  
ns  
µs  
µs  
SU,STO  
t
(Note 2)  
0.9  
HD,DAT  
Data Setup Time  
t
100  
1.3  
0.7  
SU,DAT  
SCL Clock Low Period  
SCL Clock High Period  
t
LOW  
t
HIGH  
Rise Time of Both SDA and SCL  
Signals, Receiving  
20 +  
0.1C  
t
(Notes 3, 4)  
(Notes 3, 4)  
300  
300  
250  
ns  
ns  
R
b
Fall Time of Both SDA and SCL  
Signals, Receiving  
20 +  
0.1C  
t
F
b
20 +  
Fall Time of SDA Transmitting  
t
(Notes 3, 4)  
(Note 5)  
ns  
ns  
pF  
ns  
µs  
F,TX  
0.1C  
b
Pulse Width of Spike Suppressed  
t
SP  
50  
Capacitive Load for Each Bus  
Line  
C
(Note 3)  
400  
b
RST Pulse Width  
t
W
500  
1
RST Rising to START Condition  
Setup Time  
t
RST  
Note 1: All parameters are tested at T = +25°C. Specifications over temperature are guaranteed by design.  
A
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge  
IL  
the undefined region of SCL’s falling edge.  
Note 3: Guaranteed by design.  
Note 4: C = total capacitance of one bus line in pF. t and t measured between 0.3 x V+ and 0.7 x V+. I 6mA.  
b
R
F
SINK  
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.  
_______________________________________________________________________________________  
3

与MAX7324AEG相关器件

型号 品牌 描述 获取价格 数据表
MAX7324AEG+ MAXIM 暂无描述

获取价格

MAX7324AEG+T MAXIM Parallel I/O Port, 0 I/O, BICMOS, PDSO24, 0.150 INCH, 0.25 INCH PITCH, ROHS COMPLIANT, MO-

获取价格

MAX7324AEG-T MAXIM 暂无描述

获取价格

MAX7324ATG MAXIM I2C Port Expander with Eight Push-Pull Outputs and Eight Inputs

获取价格

MAX7324ATG+ MAXIM Parallel I/O Port, 0 I/O, BICMOS, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WGGD-2, TQFN-

获取价格

MAX7324ATG+T MAXIM Parallel I/O Port, 16 I/O, BICMOS, TQFN-24

获取价格