Datasheet > MAX7323AEE+T

MAX7323AEE+T

更新时间： 2024-02-20 02:11:58

品牌	Logo	应用领域
美信 - MAXIM		光电二极管外围集成电路
页数	文件大小	规格书
15页	869K
描述
Parallel I/O Port, 8-Bit, 4 I/O, CMOS, PDSO16, 0.150 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-137, QSOP-16

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MAX7323AEE+T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP, SSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	5.35	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	4.89 mm
湿度敏感等级：	1	位数：	8
I/O 线路数量：	4	端口数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	1.8/5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Parallel IO Port	最大供电电压：	5.5 V
最小供电电压：	1.71 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：	1

MAX7323AEE+T 数据手册

MAX7323

I²C Port Expander with 4 Push-Pull

Outputs and 4 Open-Drain I/Os

Table 2. Read and Write Access to Eight-Port Expander Family

OPEN-

DRAIN

PUSH-

PULL

I C SLAVE

INTERRUPT

MASK

PART

INPUTS

I C DATA WRITE

I C DATA READ

ADDRESS

110xxxx

101xxxx

110xxxx

OUTPUTS OUTPUTS

<I7–I0 interrupt

mask>

<I7–I0 port inputs>

MAX7319

MAX7320

MAX7321

—

Yes

—

<I7–I0 transition flags>

<O7–O0 port

outputs>

<O7-O0 port inputs>

<P7–P0 port

outputs>

<P7–P0 port inputs>

Up to 8

—

Up to 8

—

<P7–P0 transition flags>

<O7, O6 outputs,

I5–I2 interrupt

mask, O1, O0

outputs>

<O7, O6, I5–I2, O1, O0 port

inputs>

MAX7322

MAX7323

110xxxx

Yes

—

<0, 0, I5–I2 transition flags,

0, 0>

<O7, O6, P5–P2, O1, O0 port

inputs>

<0, 0, P5–P2 transition flags,

0, 0>

Up to 4

<P7–P0 port

outputs>

MAX7328

MAX7329

0100xxx

0111xxx

Up to 8

—

Up to 8

—

<P7–P0 port inputs>

<P7–P0 port

outputs>

connected to the bus, including the MAX7323. This is

guaranteed as part of the I C specification. Therefore,

Slave Address and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7323

slave address, select which inputs have pullup resistors,

and set the default logic state on outputs. Pullups are

enabled on the input ports in groups of two (see Table 3).

The MAX7319, MAX7321, MAX7322, and MAX7323 use

a different range of slave addresses (110xxxx) than the

MAX7320 (101xxxx).

address inputs AD2 and AD0 that are connected to SDA

or SCL normally appear at power-up to be connected to

V+. The pullup selection logic uses AD0 to select whether

pullups are enabled for ports P2 and P3, and to set the

initial logic state for O0 and O1. AD2 selects whether

pullups are enabled for ports P4 and P5 and sets the

initial logic state for O6 and O7. The rule is that a

logic-high, SDA, or SCL connection selects the

pullups and sets the default logic state to high. A logic-low

deselects the pullups and sets the default logic state

low (see Table 3). The port configuration is correct on

The MAX7323 slave address is determined on each I C

transmission, regardless of whether the transmission

is actually addressing the MAX7323. The MAX7323

distinguishes whether address inputs AD2 and AD0 are

connected to SDA or SCL instead of fixed logic levels V+

or GND during this transmission. Therefore, the MAX7323

slave address can be configured dynamically in the

application without cycling the device supply.

power-up for a standard I C configuration, where SDA

or SCL are pulled up to V+ by the external I C pullup

resistors.

There are circumstances where the assumption that

SDA = SCL = V+ on power-up is not true—for example,

in applications in which there is legitimate bus activity

during power-up. Also, if SDA and SCL are terminated

with pullup resistors to a different supply voltage than the

MAX7323’s supply voltage, and if that pullup supply rises

later than the MAX7323’s supply, then SDA or SCL may

appear at power-up to be connected to GND. In such

applications, use the four address combinations that are

selected by connecting address inputs AD2

On initial power-up, the MAX7323 cannot decode

address inputs AD2 and AD0 fully until the first I C

transmission. AD0 and AD2 initially appear to be

connected to V+ or GND. This is important because

the address selection determines the power-up default

states of the output ports and I/O port initial logic

state, and whether pullups are enabled. However, at

power-up, theI CSDAandSCLbusinterfacelinesarehigh

impedance at the pins of every device (master or slave)

Maxim Integrated

│ 7

www.maximintegrated.com

1...4 5 678 9 10...15

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与MAX7323AEE+T相关器件

型号	品牌	描述	获取价格	数据表
MAX7323AEE-T	MAXIM	Parallel I/O Port, 8-Bit, 4 I/O, CMOS, PDSO16, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-	获取价格
MAX7323ATE	MAXIM	I2C Port Expander with 4 Push-Pull Outputs	获取价格
MAX7323ATE+	ROCHESTER	4 I/O, PIA-GENERAL PURPOSE, QCC16, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WEED-2,	获取价格
MAX7323ATE+	MAXIM	Parallel I/O Port, 8-Bit, 4 I/O, CMOS, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WEE	获取价格
MAX7324	MAXIM	I2C Port Expander with Eight Push-Pull Outputs and Eight Inputs	获取价格
MAX7324	ADI	I2C端口扩展器，提供8路推挽式输出和8路输入	获取价格

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