2
MAX7321
I C Port Expander with 8 Open-Drain I/Os
Port and Interrupt INT Timing Characteristics
(V+ = +1.71V to +5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T = +25°C.) (Note 1)
A
A
PARAMETER
Port Output Data Valid
Port Input Setup Time
Port Input Hold Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
C ≤ 100pF
4
PPV
L
t
C ≤ 100pF
0
4
µs
PSU
L
t
C ≤ 100pF
µs
PH
L
INT Input Data Valid Time
t
C ≤ 100pF
4
4
µs
IV
IP
L
INT Reset Delay Time from STOP
t
C ≤ 100pF
µs
L
INT Reset Delay Time from
t
C ≤ 100pF
4
µs
IR
L
Acknowledge
Timing Characteristics
(V+ = +1.71V to +5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
f
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
0.6
µs
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD, STA
Repeated START Condition Setup
Time
t
0.6
0.6
SU, STA
STOP Condition Setup Time
Data Hold Time
t
µs
µs
ns
µs
µs
SU, STO
t
(Note 2)
0.9
HD, DAT
Data Setup Time
t
100
1.3
0.7
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
(Notes 3, 4)
(Notes 3, 4)
300
300
250
ns
ns
R
b
Fall Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
F
b
20 +
Fall Time of SDA, Transmitting
Pulse Width of Spike Suppressed
t ,
F TX
(Notes 3, 4)
(Note 5)
ns
ns
pF
ns
µs
0.1C
b
t
50
SP
Capacitive Load for Each Bus
Line
C
t
(Note 3)
400
b
RST Pulse Width
500
1
W
RST Rising to START Condition
Setup Time
t
RST
Note 1: All parameters tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to
IL
bridge the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4:
C
= total capacitance of one bus line in pF. I
≤ 6mA. t and t measured between 0.3 x V+ and 0.7 x V+.
b
SINK R F
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Maxim Integrated
│ 3
www.maximintegrated.com