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MAX5865E/D PDF预览

MAX5865E/D

更新时间： 2024-01-13 20:25:01
品牌 Logo 应用领域
美信 - MAXIM 电信集成电路蜂窝电话电路电信电路
页数 文件大小 规格书
26页 2143K
描述
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End

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MAX5865E/D 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：7 X 7 MM, 0.80 MM HEIGHT, TQFN-48针数：48
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.12Is Samacsys：N
模拟输入最大值：1.5 V输入类型：DIFFERENTIAL
JESD-30 代码：S-XQCC-N48JESD-609代码：e0
长度：7 mm信道数量：2
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出：VOLTAGE输出代码：OFFSET BINARY
最大输出电压：3 V封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8,3.3 V
认证状态：Not Qualified分辨率：8 µm
座面最大高度：0.8 mm子类别：Codecs
标称供电电压：3 V表面贴装：YES
技术：CMOS电信集成电路类型：RF AND BASEBAND CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

MAX5865E/D 数据手册

 浏览型号MAX5865E/D的Datasheet PDF文件第2页浏览型号MAX5865E/D的Datasheet PDF文件第3页浏览型号MAX5865E/D的Datasheet PDF文件第4页浏览型号MAX5865E/D的Datasheet PDF文件第5页浏览型号MAX5865E/D的Datasheet PDF文件第6页浏览型号MAX5865E/D的Datasheet PDF文件第7页 
19-2916; Rev 1; 10/03  
Ultra-Low-Power, High-Dynamic-  
Performance, 40Msps Analog Front End  
General Description  
Features  
o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs  
o Ultra-Low Power  
The MAX5865 ultra-low-power, highly integrated analog  
front end is ideal for portable communication equipment  
such as handsets, PDAs, WLAN, and 3G wireless termi-  
nals. The MAX5865 integrates dual 8-bit receive ADCs  
and dual 10-bit transmit DACs while providing the high-  
est dynamic performance at ultra-low power. The ADCs’  
analog I-Q input amplifiers are fully differential and  
75.6mW at f  
64mW at f  
= 40MHz (Transceiver Mode)  
= 22MHz (Transceiver Mode)  
CLK  
CLK  
Low-Current Idle and Shutdown Modes  
o Excellent Dynamic Performance  
accept 1V  
full-scale signals. Typical I-Q channel  
P-P  
48.4dB SINAD at f = 5.5MHz (ADC)  
IN  
phase matching is 0.2° and amplitude matching is  
70dB SFDR at f  
= 2.2MHz (DAC)  
OUT  
0.05dB. The ADCs feature 48.4dB SINAD and 70dBc  
spurious-free dynamic range (SFDR) at f = 5.5MHz and  
IN  
o Excellent Gain/Phase Match  
f
= 40MHz. The DACs’ analog I-Q outputs are fully  
CLK  
0.2° Phase, 0.05dB Gain at f = 5.5MHz (ADC)  
IN  
differential with 400mV full-scale output, and 1.4V com-  
mon-mode level. Typical I-Q channel phase matching is  
0.15° and gain matching is 0.05dB. The DACs also  
feature dual 10-bit resolution with 72dBc SFDR, and  
o Internal/External Reference Option  
o +1.8V to +3.3V Digital Output Level (TTL/CMOS  
Compatible)  
57dB SNR at f  
= 2.2MHz and f  
= 40MHz.  
OUT  
CLK  
o Multiplexed Parallel Digital Input/Output for  
The ADCs and DACs operate simultaneously or indepen-  
dently for frequency-division duplex (FDD) and time-divi-  
sion duplex (TDD) modes. A 3-wire serial interface  
controls power-down and transceiver modes of opera-  
ADCs/DACs  
o Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)  
o Evaluation Kit Available (Order MAX5865EVKIT)  
tion. The typical operating power is 75.6mW at f  
=
CLK  
40Msps with the ADCs and DACs operating simultane-  
ously in transceiver mode. The MAX5865 features an  
internal 1.024V voltage reference that is stable over the  
entire operating power-supply range and temperature  
range. The MAX5865 operates on a +2.7V to +3.3V ana-  
log power supply and a +1.8V to +3.3V digital I/O power  
supply for logic compatibility. The quiescent current is  
8.5mA in idle mode and 1µA in shutdown mode. The  
MAX5865 is specified for the extended (-40°C to +85°C)  
temperature range and is available in a 48-pin thin QFN  
package.  
Functional Diagram  
IA+  
ADC  
IA-  
ADC  
OUTPUT  
MUX  
DA0–DA7  
QA+  
QA-  
ADC  
CLK  
Applications  
Narrowband/Wideband CDMA Handsets  
and PDAs  
ID+  
ID-  
DAC  
DAC  
DAC  
INPUT  
MUX  
DD0–DD9  
QD+  
QD-  
Fixed/Mobile Broadband Wireless Modems  
3G Wireless Terminals  
REFP  
COM  
REFN  
Ordering Information  
SERIAL  
INTERFACE  
AND SYSTEM  
CONTROL  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
DIN  
SCLK  
CS  
REF AND  
BIAS  
48 Thin QFN-EP*  
(7mm x 7mm)  
REFIN  
MAX5865ETM  
MAX5865E/D  
Dice**  
*EP = Exposed paddle.  
**Contact factory for dice specifications.  
MAX5865  
Pin Configuration appears at end of data sheet.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
1234567...26

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