Datasheet > MAX3880ECB-T

MAX3880ECB-T

更新时间： 2024-01-20 11:09:09

品牌	Logo	应用领域
美信 - MAXIM		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
12页	277K
描述
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64

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MAX3880ECB-T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	HTFQFP, TQFP64,.47SQ
针数：	64	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.44
应用程序：	SONET;SDH	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HTFQFP	封装等效代码：	TQFP64,.47SQ
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	245	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.38 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SERIAL TO PARALLEL/PARALLEL TO SERIAL CONVERTER	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

MAX3880ECB-T 数据手册

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

dropped, shifting the alignment between PCLK and

clock is derived by sampling the in-phase and quadra-

ture VCO outputs on both edges of the data input sig-

nal. Depending on the polarity of the frequency

difference, the FD drives the VCO until the frequency

difference is reduced to zero. Once frequency acquisi-

tion is complete, the FD returns to a neutral state. False

locking is completely eliminated by this digital frequen-

cy detector.

data by 1 bit. The SYNC signal must be at least four

serial bit periods wide (4 x 402ps). See Figure 4 for the

timing diagram and Figure 5 for the timing parameters

diagram.

Input Amplifier

The input amplifiers on both the main data and system

loopback accept a differential input amplitude from

50mVp-p to 800mVp-p. The bit error rate (BER) is bet-

ter than 1 x 10^-10for input signals as small as 9.5mVp-

p, although the jitter tolerance performance will be

degraded. For interfacing with PECL signal levels, see

Applications Information.

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. A 1.0µF capacitor, C , is

required to set the PLL damping ratio.

The loop filter output controls the on-chip LC VCO run-

ning at 2.488GHz. The VCO provides low phase noise

and is trimmed to the correct frequency.

Phase Detector

The phase detector in the MAX3880 produces a volt-

age proportional to the phase difference between the

incoming data and the internal clock. Because of its

feedback nature, the PLL drives the error voltage to

zero, aligning the recovered clock to the center of the

incoming data eye for retiming. The external phase

adjust pins (PHADJ+, PHADJ-) allow the user to vary

the internal phase alignment.

Loss-of-Lock Monitor

A loss-of-lock (LOL) monitor is included in the

MAX3880 frequency detector. A loss-of-lock condition

is signaled immediately with a TTL low. When the PLL is

frequency-locked, LOL switches to TTL high in approxi-

mately 800ns.

Note that the LOL monitor is only valid when a data

stream is present on the inputs to the MAX3880. As a

result, LOL does not detect a loss-of-power condition

resulting from a loss of the incoming signal.

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during start-up conditions. The frequency

difference between the received data and the VCO

D15 D14

D13

SDI

SYNC

PCLK

D16

D17

D32

D33

D48

D49

D65

D66

(LSB) PD0

PD1

•

1 BIT HAS SLIPPED

IN THIS TIME SLICE

D15

D31

D47

D64

D80

PD15

(MSB)

TRANSMITTED FIRST

Figure 4. Timing Diagram

_______________________________________________________________________________________

1...4 5 678 9 10...12

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与MAX3880ECB-T相关器件

型号	品牌	描述	获取价格	数据表
MAX3880ECB-TD	MAXIM	Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT,	获取价格
MAX3880EVKIT	MAXIM	Evaluation Kit for the MAX3880	获取价格
MAX3881	MAXIM	+3.3V.2.488Gbps.SDH/SONET 1:16 Deserializer with Clock Recovery	获取价格
MAX3881ECB	MAXIM	+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery	获取价格
MAX3881ECB+D	MAXIM	ATM/SONET/SDH Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, RO	获取价格
MAX3881ECB+TD	MAXIM	Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT,	获取价格

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