MAX38640/1/2/3/A/B
Tiny 1.8V - 5.5V Input, 330nA I , 700mA
Q
nanoPower Buck Converter
Absolute Maximum Ratings
IN, EN, RSEL, NC, OUT to GND.............................. -0.3V to +6V
4.5mW/°C above +70°C) ...............................................357.8mW
Operating Temperature Range.............................-40°C to +85°C
Maximum Junction Temperature ......................................+150°C
Storage Temperature Range ..............................-65°C to +150°C
Lead Temperature (soldering, 10 seconds)......................+300ºC
Soldering Temperature (reflow) ........................................+260°C
LX RMS Current WLP ............................. -1.6A
LX RMS Current µDFN.................................. -1A
to +1.6A
RMS
RMS
RMS
to +1A
RMS
Continuous Power Dissipation - WLP (T = +70°C) (Derate
A
10.5mW/°C above +70°C)................................................ 840mW
Continuous Power Dissipation – µDFN (T = +70°C) (Derate
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Package Information
6 µDFN
Package Code
L622+1C
21-0164
90-0004
Outline Number
Land Pattern Number
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θ
)
223.6°C/W
122°C/W
JA
Junction-to-Case Thermal Resistance (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
6 WLP
Package Code
Outline Number
N60E1+2
21-100128
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θ
)
JA
95.15°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
www.maximintegrated.com
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