2.7Gbps Laser Driver with Modulation
Compensation
MAX863
V
CC
A - TOKO FSLB2520-330K
B - MURATA BLM11HA601SPT
A
B
A
B
V
V
CC
CC
50Ω
50Ω
DATA+
DATA-
DATA+
DATA-
25Ω
MODN
0.1μF
V
OSCILLOSCOPE
CC
MAX3863
V
CC
50Ω
MOD
0.1μF
APCFILT1
50Ω
50Ω
CLK+
CLK-
CLK+
CLK-
50Ω
50Ω
V
CC
BIAS
EN
RTEN
15Ω
Figure 1. AC Characterization
Mark-Density Outputs
Detailed Description
The MK+ and MK- outputs monitor the input signal
mark density. With a 50% mark density, both outputs
are the same voltage. More ones cause the MK+ volt-
age to increase and the MK- voltage to decrease.
Fewer ones than zeros cause MK- to be at a higher
voltage than MK+.
The MAX3863 laser driver has two main components: a
high-speed modulation driver and a biasing block with
APC. The clock and data inputs to the modulation driver
use CML logic levels. The optional clock signal synchro-
nizes data transitions for minimum pattern-dependent jit-
ter. Outputs to the laser diode consist of a switched
modulation current and a steady bias current. The APC
loop adjusts the laser diode bias current to maintain con-
stant average optical power. Compensation of the modu-
lation current can be programmed to keep a constant
extinction ratio over time and temperature. The modula-
tion output stage uses a programmable current source
with a maximum current of 80mA. A high-speed differen-
tial pair switches the source to the laser diode. The rise
and fall times are typically 50ps.
Pulse-Width Control
A pulse-width adjustment range of 50% to 150%
( 185ps) is available at 2.7Gbps. This feature compen-
sates pulse-width distortion elsewhere in the system.
Resistors at the PWC+ and PWC- pins program the
pulse width. The sum of the resistors is 1kΩ. The pins
can be left open for a 100% pulse width. A voltage also
can control these pins. A differential voltage of 600mV
(typ) gives 185ps of pulse-width distortion.
Optional Input Data Retiming
To eliminate pattern-dependent jitter in the input data, a
synchronous differential clock signal should be con-
nected to the CLK+ and CLK- inputs, and the RTEN
control input should be connected low. The input data
is retimed on the rising edge of CLK+. If RTEN is tied
high or is left floating, the retiming function is disabled,
and the input data is directly connected to the output
stage. Leave CLK+ and CLK- open when retiming is
disabled.
Output Enable
The MAX3863 incorporates an input to enable current
to the laser diode. When EN is low, the modulation and
bias outputs at the MOD pin are enabled. When EN is
high or floating, the output is disabled. In the disabled
condition, bias and modulation currents are off.
Power-Supply Threshold
To prevent data errors caused by low supply, the
MAX3863 disables the laser diode current for supply
voltage less than 2.7V. The power-supply threshold and
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