2.7Gbps Post Amp with Automatic Gain Control
Pin Description
PIN
NAME
FUNCTION
Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to
program the input signal detect assert threshold. Leaving this pin open sets the signal detect
1
TH
threshold to its absolute minimum value (<2mV ). See the Design Procedure section.
P-P
2, 5, 14, 17
V
Supply Voltage Connection. Connect all V
pins to the board V
plane.
CC
CC
CC
3
4
IN+
IN-
Positive CML Signal Input with On-Chip Termination Resistor
Negative CML Signal Input with On-Chip Termination Resistor
Signal Detect Enable. Set high (≥2.0V) or leave open to enable the input signal detection (RSSI and
SD) circuitry. Set low (≤0.4V) to power-down the input signal detection circuitry.
6
EN
VREF
SC
7
Reference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing.
Output Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or
connect SC directly to VREF for maximum output amplitude.
8
9, 12, 22
10
GND
CG+
Ground. Connect all GND pins to the board ground plane.
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
11
CG-
13
15
16
OSM
OUT-
OUT+
Output Signal Monitor. This DC signal is linearly proportional to the output signal amplitude.
Negative CML Data Output with On-Chip Back-Termination Resistor
Positive CML Data Output with On-Chip Back-Termination Resistor
Input Signal Detect. Asserts logic low when the input signal level drops below the programmed
threshold.
18
19
SD
Received Signal Strength Indicator. Outputs a DC signal that is linearly proportional to the input
signal amplitude.
RSSI
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
20
21
23
CD-
CD+
CZ-
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
24
EP
CZ+
Exposed Pad Maxim recommends connecting the exposed pad to board ground.
6
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