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MAX3772 PDF预览

MAX3772

更新时间: 2024-02-09 18:59:10
品牌 Logo 应用领域
美信 - MAXIM 光纤
页数 文件大小 规格书
9页 221K
描述
Dual-Rate Fibre Channel Repeaters

MAX3772 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:HLSSOP,
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.87JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:4.89 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HLSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):245
认证状态:Not Qualified座面最大高度:1.65 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm

MAX3772 数据手册

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Dual-Rate Fibre Channel Repeaters  
0.047µF  
CF+  
CF-  
V
CC  
D
Q
OUT+  
OUT-  
IN+  
IN-  
OPTIONAL  
50OR 75Ω  
PHASE/FREQ  
DETECTOR  
LOOP  
FILTER  
1
0
VCO  
V
CC  
÷2  
OPTIONAL  
100OR 150Ω  
TERMINATION  
CLK+  
CLK-  
RATESEL  
CLKEN  
LOCK  
Figure 2. Block Diagram  
See the Applications Information section for the func-  
Loop Filter, VCO, and Latch  
The phase detector and frequency detector outputs are  
summed into a loop filter. An external capacitor  
(between CF+ and CF-) is required to set the PLL  
damping factor. The fully integrated VCO contains an  
internal current reference and filter circuitry to minimize  
tionality of the RATESEL pin.  
Applications Information  
Input and Output Terminations  
Figures 3 and 4 show models for the MAX3772–  
MAX3775 inputs and outputs, including packaging parasitics.  
the influence of V  
noise. The VCO creates a clock  
CC  
output with frequency proportional to the control volt-  
age applied by the loop filter. Data recovery is accom-  
plished by using the recovered clock signal to latch the  
incoming data to the CML output buffers, significantly  
reducing output jitter.  
V
CC  
ESD  
STRUCTURES  
LOCK Output  
An active high LOCK output monitor derived from the  
frequency detector indicates that the PLL is frequency-  
locked onto the input data. Without input data, the  
LOCK signal may settle high or low. The use of a low-  
pass RC filter is recommended to reduce the effects of  
chatter that could be caused by high input-jitter con-  
tent. For optimum jitter performance, keep the load  
15kon the output of the LOCK pin.  
PACKAGE  
1.5nH  
1kΩ  
IN+  
0.2pF  
0.4pF  
1.5nH  
0.2pF  
0.4pF  
RATESEL Input  
The RATESEL input is used to select between input  
data rates of 2.125Gbps and 1.0625Gbps. This func-  
tion allows the repeater to sample data at the correct  
data rate by selecting a divide-by-2 network, giving  
maximum jitter tolerance at both data rates. The loop  
bandwidth of the repeater scales with the selected fre-  
quency; i.e., the loop-bandwidth at an input rate of  
1.0625Gbps is half that at the input rate of 2.125Gbps.  
V
- 0.450V  
CC  
OPTIONAL  
50OR 75Ω  
Figure 3. Input Structure  
_______________________________________________________________________________________  
7

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