MAX3772

更新时间： 2024-02-07 12:08:58

品牌	Logo	应用领域
美信 - MAXIM		光纤
页数	文件大小	规格书
9页	221K
描述
Dual-Rate Fibre Channel Repeaters

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技术参数
数据手册

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MAX3772 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	HLSSOP,
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.87	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	4.89 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	HLSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	245
认证状态：	Not Qualified	座面最大高度：	1.65 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm

MAX3772 数据手册

Dual-Rate Fibre Channel Repeaters

Pin Description

NAME

CF+

CF-

FUNCTION

CDR Filter Capacitor Positive Connection. C = 0.047µF.

CDR Filter Capacitor Negative Connection. C = 0.047µF.

3, 6, 12

GND

IN+

Electrical Ground

Noninverted Data Input

Inverted Data Input

Supply Voltage

IN-

7, 8

RATESEL Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation.

OUT-

OUT+

CLKEN

CLK-

Inverted Data Output

Noninverted Data Output

Clock Output Enable. TTL high enables the clock output. TTL low disables the clock output.

Inverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low.

Noninverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low.

CLK+

Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequency-locked.

The output of the LOCK pin may chatter when large jitter is applied to the input.

LOCK

Exposed

Paddle

The exposed paddle must be soldered to the circuit board ground for proper thermal performance.

Detailed Description

Figure 2 shows the functional block diagram of the

MAX3772–MAX3775 fibre channel repeaters. They con-

sist of a fully integrated PLL, CML input and output

buffers, and a data latch. The PLL consists of a com-

OUT

bined phase detector (PD) and frequency detector

500mVp-p MIN

900mVp-p MAX

(FD), a loop filter, and a voltage-controlled oscillator

(VCO). The input and output signal buffers employ low-

noise CML architecture and are terminated on-chip.

OUT

(V +) - (V -)

OUT

Phase and Frequency Detector

The frequency difference between the VCO clock and

1000mVp-p MIN

1800mVp-p MAX

the received data is derived by sampling the in-phase

and quadrature VCO outputs on the edges of the input

data signal. The FD drives the VCO until the frequency

difference is reduced to zero. Once frequency acquisi-

tion is complete, the PD produces a voltage proportion-

al to the phase difference between the incoming data

and the internal clock. The PLL drives this error voltage

to zero, aligning the recovered clock to the center of

the incoming eye.

Figure 1. Example of Output Signal with Matched Output Loads

_______________________________________________________________________________________

1...3 4 567 8 9

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与MAX3772相关器件

型号	品牌	描述	获取价格	数据表
MAX3772CEE	MAXIM	Dual-Rate Fibre Channel Repeaters	获取价格
MAX3772CEE+	MAXIM	Telecom Circuit, 1-Func, PDSO16, 0.150 INCH, LEAD FREE, QSOP-16	获取价格
MAX3772CEE+T	MAXIM	Telecom Circuit, 1-Func, PDSO16, 0.150 INCH, LEAD FREE, QSOP-16	获取价格
MAX3772CEE-T	MAXIM	Telecom Circuit, 1-Func, PDSO16, 0.150 INCH, QSOP-16	获取价格
MAX3772EVKIT	MAXIM	Evaluation Kits for the MAX3772/MAX3773/MAX3774/MAX3775	获取价格
MAX3773	MAXIM	Dual-Rate Fibre Channel Repeaters	获取价格

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