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MAX3748 PDF预览

MAX3748

更新时间: 2024-02-27 15:47:42
品牌 Logo 应用领域
美信 - MAXIM 放大器
页数 文件大小 规格书
11页 415K
描述
Compact 155Mbps to 3.2Gbps Limiting Amplifier

MAX3748 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC16,.12SQ,20针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.42应用程序:ATM;SONET
JESD-30 代码:S-XQCC-N16JESD-609代码:e0
长度:3 mm功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.049 mA
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmBase Number Matches:1

MAX3748 数据手册

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Compact 155Mbps to 3.2Gbps  
Limiting Amplifier  
Pin Description  
PIN  
NAME  
FUNCTION  
1, 4, 12  
V
Supply Voltage  
CC  
2
3
IN+  
IN-  
Noninverted Input Signal, CML  
Inverted Input Signal, CML  
Loss-of-Signal Threshold Pin. Resistor to ground (R ) sets the LOS threshold. Connecting this pin to  
TH  
5
TH  
V
disables the LOS circuitry and reduces power consumption.  
CC  
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS  
function remains active when the outputs are disabled, CMOS. On the MAX3748, this pin does not  
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection  
is required. On the MAX3748A, this pin has ESD protection.  
6
DISABLE  
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert  
threshold set by the TH input. The output is open collector (Figure 5). On the MAX3748, this pin does not  
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection  
is required. On the MAX3748A, this pin has ESD protection.  
7
LOS  
8, 16  
9
GND  
Supply Ground  
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier  
and connect to V  
OUTPOL  
for normal operation.  
CC  
10  
11  
OUT-  
Inverted Data Output, CML  
OUT+  
Noninverted Data Output, CML  
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced  
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor between  
this pin and GND.  
13  
14  
RSSI  
CAZ2  
CAZ1  
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1  
extends the time constant of the offset correction loop. Typical value of C is 0.1µF. The offset  
AZ  
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.  
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends  
the time constant of the offset correction loop. Typical value of C is 0.1µF. The offset correction is disabled  
AZ  
when the CAZ1 and CAZ2 pins are shorted together.  
15  
EP  
Exposed  
paddle  
Connect the exposed paddle to board ground for optimal electrical and thermal performance.  
Detailed Description  
V
CC  
The limiting amplifier consists of an input buffer, a multi-  
stage amplifier, offset correction circuitry, an output  
buffer, power-detection circuitry, and signal-detect cir-  
cuitry (see Functional Diagram).  
I
(CML  
OUT  
OUTPUT CURRENT)  
I
(SUPPLY CURRENT)  
50  
CC  
50  
Input Buffer  
The input buffer is shown in Figure 3. It provides 50  
termination for each input signal IN+ and IN-. The  
MAX3748/MAX3748A can be DC- or AC-coupled to a  
TIA (TIA output offset degrades receiver performance if  
DC-coupled). The CML input buffer is optimized for the  
MAX3744 TIA.  
MAX3748/  
MAX3748A  
R
TH  
Gain Stage  
The high-bandwidth gain stage provides approximately  
53dB of gain.  
Figure 1. Power-Supply Current Measurement  
6
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