MAX3747EUB-T

更新时间： 2024-02-17 06:18:41

品牌	Logo	应用领域
美信 - MAXIM		放大器
页数	文件大小	规格书
10页	360K
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数据手册

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MAX3747EUB-T 数据手册

155Mbps to 3.2Gbps, Low-Power SFP

Limiting Amplifiers

Pin Description

MAX3747/

MAX3747A

MICREL

SY8893V

FUNCTION

NAME

Disable Function Pin. The data outputs are held static when this pin is asserted high,

transistor-to-transistor logic (TTL).

DISABLE

IN+

IN-

DIN

Noninverted Input Signal, CML

DIN

Inverted Input Signal, CML

Reference Voltage for LOS Threshold Setting

REF

Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets

the threshold level. Connect one resistor from this pin to V

and another from this pin

LOSLVL

GND

to V

(see Figure 5).

REF

GND

LOS

Ground

Loss-of-Signal, Open Collector. LOS is high when the level of the input signal drops

below the preset threshold set by the TH input. LOS is deasserted low when the signal

level is above the threshold.

LOS

OUT-

DOUT

Inverted Data Output, CML

Noninverted Data Output, CML

Positive Power Supply

OUT+

DOUT

Detailed Description

The limiting amplifiers consist of a multistage amplifier,

offset-correction circuitry, an output buffer, and loss-of-

signal detect circuitry (see the Functional Diagram).

Input Stage

MAX3747

MAX3747A

The input stage is shown in Figure 3. It provides 50Ω

termination to V

for each input signal, IN+ and IN-.

The MAX3747/MAX3747A should be AC-coupled.

REF

Multistage Amplifier

The high-bandwidth multistage amplifier provides

approximately 57dB of gain for the MAX3747 and 61dB

of gain for the MAX3747A.

ESD

STRUCTURES

Offset Correction Loop

The MAX3747/MAX3747A are susceptible to DC offsets

in the signal path because they have high gain. In com-

munication systems using NRZ data with a 50% duty

cycle, pulse-width distortion present in the signal or gen-

erated in the transimpedance amplifier appears as an

input offset and is reduced by the offset correction loop.

50Ω

REF

The offset correction loop sets a low-frequency cutoff of

3.2kHz.

Figure 3. CML Input Stage

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