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MAX3675ECJ+T

更新时间： 2024-01-20 08:39:48
品牌 Logo 应用领域
美信 - MAXIM 放大器时钟
页数 文件大小 规格书
16页 192K
描述
Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, TQFP-32

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MAX3675ECJ+T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：TFQFP,
针数：32Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.9
应用程序：ATM;SDH;SONETJESD-30 代码：S-PQFP-G32
JESD-609代码：e0长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.2 mm
标称供电电压：3.3 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

MAX3675ECJ+T 数据手册

 浏览型号MAX3675ECJ+T的Datasheet PDF文件第4页浏览型号MAX3675ECJ+T的Datasheet PDF文件第5页浏览型号MAX3675ECJ+T的Datasheet PDF文件第6页浏览型号MAX3675ECJ+T的Datasheet PDF文件第8页浏览型号MAX3675ECJ+T的Datasheet PDF文件第9页浏览型号MAX3675ECJ+T的Datasheet PDF文件第10页 
6 2 2 Mb p s , Lo w -P o w e r, 3 .3 V Clo c k -Re c o ve ry  
a n d Da t a -Re t im in g IC w it h Lim it in g Am p lifie r  
MAX3675  
LOL  
PHADJ+ PHADJ- FIL+ FIL-  
V
CC  
6k  
SDO+  
SDO-  
D
Q
PECL  
PECL  
DDI+  
DDI-  
SCLKO+  
SCLKO-  
I
PHASE/FREQ  
DETECTOR  
PECL  
FILTER  
VCO  
Σ
Q
INSEL  
622.08MHz  
V
CC  
ADI-  
1.18V  
LIMITER  
42dB  
BIAS  
6k  
ADI+  
POWER  
DETECT  
OFFSET  
CORRECTION  
MAX3675  
OLC+ OLC-  
CFILT  
RSSI INV  
VTH  
LOP  
Figure 1. Functional Diagram  
100µV  
amplitude data streams.  
, providing excellent sensitivity for small-  
RMS  
_______________De t a ile d De s c rip t io n  
The block diagram in Figure 1 shows the MAX3675’s  
architecture. It consists of a limiting amplifier input  
stage followed by a fully integrated clock/data-recovery  
(CDR) block implemented with a phase-locked loop  
(PLL). The input stage is selectable between a limiting  
amplifier or a simple PECL input buffer. The limiting  
amplifier provides a loss-of-power (LOP) monitor and a  
received-signal-strength indicator (RSSI). The PLL con-  
sists of a phase/frequency detector (PFD), a loop filter  
amplifier, and a voltage-controlled oscillator (VCO).  
In addition to driving the CDR, the limiting amplifier pro-  
vides both an RSSI output and an LOP monitor that  
allow the user to program the threshold voltage. The  
RSSI circuitry provides an output voltage that is linearly  
proportional to the input power (in decibels) detected  
between the ADI+ and ADI- input pins and is sensitive  
enough to reliably detect signals as small as 2mVp-p.  
Input DC offset reduces the accuracy of the power  
detector; therefore, an integrated feedback loop is  
included that automatically nulls the input offset of the  
gain stage. The addition of this offset-correction loop  
requires that the input signal be AC coupled when  
using the ADI+ and ADI- inputs.  
Lim it in g Am p lifie r  
The MAX3675’s on-chip limiting amplifier accepts an  
input signal level from 3.0mVp-p to 1.2Vp-p. The ampli-  
fier consists of a cascade of gain stages that include  
full-wave logarithmic detectors. The combined small-  
signal gain is approximately 42dB, and the -3dB band-  
wid th is 800MHz. Inp ut-re fe rre d nois e is le s s tha n  
Finally, for applications that do not require the limiting  
amplifier, selecting the digital inputs conserves power  
by turning off the post-amplifier block.  
_______________________________________________________________________________________  
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