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MAX3645ESE-T

更新时间： 2024-01-27 15:17:14
品牌 Logo 应用领域
美信 - MAXIM ATM异步传输模式电信光电二极管电信集成电路
页数 文件大小 规格书
10页 262K
描述
Support Circuit, 1-Func, Bipolar, PDSO16, 0.150 INCH, MS-012AC, SOIC-16

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MAX3645ESE-T 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：0.150 INCH, MS-012AC, SOIC-16针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.42应用程序：SONET
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：9.9 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：245电源：3.3/5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：ATM/SONET/SDH ICs最大压摆率：0.027 mA
标称供电电压：3.3 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

MAX3645ESE-T 数据手册

 浏览型号MAX3645ESE-T的Datasheet PDF文件第3页浏览型号MAX3645ESE-T的Datasheet PDF文件第4页浏览型号MAX3645ESE-T的Datasheet PDF文件第5页浏览型号MAX3645ESE-T的Datasheet PDF文件第7页浏览型号MAX3645ESE-T的Datasheet PDF文件第8页浏览型号MAX3645ESE-T的Datasheet PDF文件第9页 
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting  
Amplifier with Loss-of-Signal Detector  
Pin Description  
MINDSPEED  
MAXIM  
MC2045-2  
MC2045-2Y  
PIN NAME  
PIN  
MAX3645  
PIN NAME  
FUNCTION  
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and  
CAZ1 sets the time constant of the offset correction loop. The offset correction is disabled  
when the CAZ1 and CAZ2 pins are shorted together.  
1
2
CAZ-  
CAZ2  
CAZ1  
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and  
CAZ2 sets the time constant of the offset correction loop. The offset correction is disabled  
when the CAZ2 and CAZ1 pins are shorted together.  
CAZ+  
GNDA  
3
4
5
6
GNDA  
DIN+  
DIN-  
Analog Supply Ground. Must be at the same potential as the GNDE pin.  
D
D
Positive Data Input  
Negative Data Input  
IN  
IN  
V
V
+2.97V to +5.5V Analog Supply Voltage. Must be at same potential as the V  
pin.  
CCA  
CCA  
CCE  
7
C
CSD  
Signal-Detect-Filter Capacitor Connection. Connect the C capacitor between CSD and V  
.
F
SD  
CCA  
Disable Input, PECL or CMOS Compatible. Data outputs are held to a static logic ꢀ when DIS is  
asserted high. The LOS function remains active when the outputs are disabled. When  
connected to the LOS pin, an automatic squelch function is enabled.  
8
JAM  
DIS  
Positive Loss-of-Signal Output, PECL. LOS is high when the level of the input signal drops  
below the threshold set by the TH input. LOS is low when the signal level is above the  
threshold. LOS can be connected directly to DIS for automatic squelch.  
9
ST  
LOS  
Negative Loss-of-Signal Output, PECL. LOS is low when the level of the input signal drops  
below the threshold set by the TH input. LOS is high when the signal level is above the  
threshold.  
1ꢀ  
ST  
LOS  
11  
12  
13  
14  
15  
GNDE  
GNDE  
DOUT-  
DOUT+  
Digital Supply Ground. Must be at the same potential as the GNDA pin.  
Negative Data Output, PECL. A high at DIS forces DOUT- high.  
Positive Data Output, PECL. A high at DIS forces DOUT+ low.  
D
OUT  
D
OUT  
V
CCE  
V
+2.97V to +5.5V Digital Supply Voltage. Must be at the same potential as the V  
pin.  
CCA  
CCE  
NC  
N.C.  
No Connection  
Loss-of-Signal Threshold Pin. Resistor (R ) to ground sets the LOS threshold. This pin cannot  
TH  
be left open.  
16  
V
SET  
TH  
tance variation (3.3kΩ to 6.4kΩ) must be considered to  
Detailed Description  
The MAX3645 consists of gain stages, offset correction,  
power detector, LOS indicators, and PECL output buffers.  
See Figure 2 for the functional diagram.  
accurately calculate the -3dB frequency. Capacitor val-  
ues should be chosen that set the -3dB frequency at  
least a factor of 1ꢀ below the lowest frequency of inter-  
est. A capacitor value of ꢀ.1µF is recommended.  
Data Input  
Gain Stage and Offset Correction  
The data inputs have a single-ended input resistance of  
The limiting amplifier provides approximately 74dB  
TH  
4.8kΩ and are internally DC-biased to V  
- ꢀ.87V (see  
CC  
(R = 1ꢀꢀΩ) of gain. This large gain makes the ampli-  
Figure 3). External capacitors are required to AC-cou-  
ple the data signals. Pattern-dependent jitter is mini-  
mized by using coupling capacitor values large enough  
to pass the lowest frequencies of interest (consecutive  
ones and zeros) with the given input resistance.  
fier susceptible to small DC offsets in the signal path.  
To correct DC offsets, the amplifier has an internal feed-  
back loop that acts as a DC autozero circuit. By cor-  
recting the DC offsets, the limiting amplifier improves  
receiver sensitivity and power-detector accuracy.  
Typically, ꢀ.1µF coupling capacitors yield a -3dB fre-  
quency of 354Hz. Capacitor tolerance and input resis-  
6
_______________________________________________________________________________________  
1...345678910

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