System Management Microcontroller
Table 2. I/O Port Pins
PRIMARY
FUNCTION
ALTERNATE
FUNCTION
PORT INDEX
INTERRUPTS
TAP (JTAG)
RESET STATE
P6.0
P6.1
P6.2
P6.3
GPIO, P6.0
GPIO, P6.1
GPIO, P6.2
GPIO, P6.3
—
INT0
INT1
INT2
INT3
TCK
TDI
TCK
TDI
—
Timer B TBB Pin
—
TMS
TDO
TMS
TDO
GPIO input with
weak pullup
P6.4
GPIO, P6.4
Timer B TBA Pin
INT4
—
V
DD
I/O PAD
WEAK
PD6.n
MAX31782
SF DIRECTION
V
DD
SF ENABLE
PO6.n
SF OUTPUT
P6.n
PI6.n OR SF INPUT
INTERRUPT
FLAG
DETECT
CIRCUIT
FLAG
EIE6.n
EIES6.n
n = 0−4
Figure 4. Port 6 I/O Block Diagram
individually by configuring the corresponding PWMRn
register and the PWMCn register, respectively.
PWM Outputs
The device provides six independent PWM outputs. Each
PWM output is associated with four SFRs: PWMCNn,
PWMVn, PWMRn, and PWMCn, where n = 0–5 is the
channel number. The PWM clock is derived from the
system clock with a division ratio defined by PWMCNn.
The PWMCNn register also enables/disables the PWM
output and selects the PWM polarity. The user can set
the frequency and the duty cycle of each PWM output
When the PWM output functionality of a PWM.n pin is
disabled, that pin can be used as a GPIO. When used
as GPIO pins, PWM.n pins are accessed as Port 1 and
through three SFRs: PO1, PI1, and PD1. Each PWM.n pin
can be independently configured, and can be defined
as an input with weak pullup, an input without pullup, or
an output.
15