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MAX1003CAX+ PDF预览

MAX1003CAX+

更新时间： 2024-01-25 08:59:00
品牌 Logo 应用领域
美信 - MAXIM 光电二极管转换器
页数 文件大小 规格书
12页 118K
描述
ADC, Flash Method, 6-Bit, 2 Func, 1 Channel, Parallel, 6 Bits Access, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36

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MAX1003CAX+ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：36
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.86最大模拟输入电压：2.75 V
最小模拟输入电压：1.75 V转换器类型：ADC, FLASH METHOD
JESD-30 代码：R-PDSO-G36JESD-609代码：e3
长度：15.415 mm最大线性误差 (EL)：0.7812%
湿度敏感等级：1模拟输入通道数量：1
位数：6功能数量：2
端子数量：36最高工作温度：70 °C
最低工作温度：输出位码：OFFSET BINARY
输出格式：PARALLEL, 6 BITS封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified采样速率：90 MHz
座面最大高度：2.64 mm标称供电电压：5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.495 mm
Base Number Matches：1

MAX1003CAX+ 数据手册

 浏览型号MAX1003CAX+的Datasheet PDF文件第2页浏览型号MAX1003CAX+的Datasheet PDF文件第3页浏览型号MAX1003CAX+的Datasheet PDF文件第4页浏览型号MAX1003CAX+的Datasheet PDF文件第6页浏览型号MAX1003CAX+的Datasheet PDF文件第7页浏览型号MAX1003CAX+的Datasheet PDF文件第8页 
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC  
MAX103  
______________________________________________________________P in De s c rip t io n  
PIN  
NAME  
FUNCTION  
1
GAIN  
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).  
Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled  
inputs. Ground for DC-coupled inputs.  
2
3
IOCC+  
IOCC-  
Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled  
inputs. Ground for DC-coupled inputs.  
4
5
6
IIN+  
IIN-  
I-Channel Noninverting Analog Input  
I-Channel Inverting Analog Input  
V
CC  
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).  
7, 11, 12,  
18, 19  
GND  
Analog Ground  
8
V
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11).  
Positive Oscillator/Clock Input  
CC  
9
TNK+  
TNK-  
10  
13  
14  
15  
Negative Oscillator/Clock Input  
V
CC  
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12).  
Q-Channel Inverting Analog Input  
QIN-  
QIN+  
Q-Channel Noninverting Analog Input  
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled  
inputs. Ground for DC-coupled inputs.  
16  
17  
QOCC-  
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled  
inputs. Ground for DC-coupled inputs.  
QOCC+  
20–25  
26, 28  
27  
DQ5–DQ0  
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).  
Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).  
Digital Output Ground  
V
CCO  
OGND  
DCLK  
29  
Digital Clock Output. Frames the output data.  
30–35  
36  
DI0–DI5  
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).  
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19).  
V
CC  
P ro g ra m m a b le In p u t Am p lifie rs  
_______________De t a ile d De s c rip t io n  
The MAX1003 has two (I and Q) programmable-gain  
input amplifiers with a -0.5dB bandwidth of 55MHz and  
true differential inputs. To maximize performance in  
high-speed systems, each amplifier has less than 5pF  
of input capacitance. The input amplifier gain is pro-  
grammed, via the GAIN pin, to provide three possible  
input full-scale ranges (FSRs) as shown in Table 1.  
Co n ve rt e r Op e ra t io n  
The MAX1003 contains two 6-bit analog-to-digital con-  
verters (ADCs), a buffered voltage reference, and oscil-  
la tor c irc uitry. The ADCs us e a fla s h c onve rs ion  
technique to convert an analog input signal into a 6-bit  
parallel digital output code. The MAX1003’s unique  
design includes 63 fully differential comparators and a  
proprietary encoding scheme that ensures no more  
than 1LSB dynamic encoding error. The control logic  
inte rfa c e s e a s ily to mos t d ig ita l s ig na l p roc e s s ors  
(DSPs) and microprocessors (µPs) with +3.3V CMOS-  
c omp a tib le log ic inte rfa c e s . Fig ure 1 s hows the  
MAX1003 in a typical application.  
Table 1. Input Amplifier Programming  
INPUT FULL-SCALE RANGE  
GAIN  
(mVp-p)  
GND  
500  
250  
125  
Open  
V
CC  
_______________________________________________________________________________________  
5
12345678...12

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