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MAX1003CAX+

更新时间： 2024-01-06 11:13:36
品牌 Logo 应用领域
美信 - MAXIM 光电二极管转换器
页数 文件大小 规格书
12页 118K
描述
ADC, Flash Method, 6-Bit, 2 Func, 1 Channel, Parallel, 6 Bits Access, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36

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MAX1003CAX+ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：36
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.86最大模拟输入电压：2.75 V
最小模拟输入电压：1.75 V转换器类型：ADC, FLASH METHOD
JESD-30 代码：R-PDSO-G36JESD-609代码：e3
长度：15.415 mm最大线性误差 (EL)：0.7812%
湿度敏感等级：1模拟输入通道数量：1
位数：6功能数量：2
端子数量：36最高工作温度：70 °C
最低工作温度：输出位码：OFFSET BINARY
输出格式：PARALLEL, 6 BITS封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified采样速率：90 MHz
座面最大高度：2.64 mm标称供电电压：5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.495 mm
Base Number Matches：1

MAX1003CAX+ 数据手册

 浏览型号MAX1003CAX+的Datasheet PDF文件第1页浏览型号MAX1003CAX+的Datasheet PDF文件第2页浏览型号MAX1003CAX+的Datasheet PDF文件第4页浏览型号MAX1003CAX+的Datasheet PDF文件第5页浏览型号MAX1003CAX+的Datasheet PDF文件第6页浏览型号MAX1003CAX+的Datasheet PDF文件第7页 
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC  
MAX103  
AC ELECTRICAL CHARACTERISTICS  
(V = +5V ±5%, V  
= 3.3V ±300mV, T = +25°C, unless otherwise noted.)  
CC  
CCO  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
= 20MHz sine, amplitude -1dB below  
INQ  
TYP  
MAX  
UNITS  
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), V = V  
INI  
full scale, unless otherwise noted.)  
Maximum Sample Rate  
f
90  
Msps  
MAX  
Analog Input -0.5dB Bandwidth  
BW  
GAIN = GND, open, V  
55  
MHz  
CC  
GAIN = open (mid gain)  
5.6  
5.85  
ENOB  
M
GAIN = open (mid gain), f = 50MHz,  
IN  
-1dB below full scale  
5.7  
Effective Number of Bits  
Bits  
ENOB  
GAIN = V (high gain)  
CC  
5.8  
H
ENOB  
GAIN = GND (low gain)  
5.85  
L
Signal-to-Noise plus Distortion  
Ratio  
SINAD  
OFF  
GAIN = open (mid gain)  
35.5  
37  
dB  
I channel  
-0.5  
-0.5  
0.5  
0.5  
Input Offset (Note 5)  
LSB  
Q channel  
Crosstalk Between ADCs  
XTLK  
OMM  
-55  
dB  
Offset Mismatch Between ADCs  
(Note 5)  
-0.5  
-0.2  
-2  
±0.25  
0.5  
0.2  
2
LSB  
Amplitude Match Between  
ADCs  
AM  
PM  
±0.1  
±0.5  
dB  
Phase Match Between ADCs  
degrees  
TIMING CHARACTERISTICS (Data outputs: R = 1MΩ, C = 15pF)  
L
L
Clock to Data Propagation  
Delay  
t
(Note 6)  
3.6  
ns  
PD  
Data Valid Skew  
Input to DCLK Delay  
Aperture Delay  
t
(Note 6)  
1.5  
5.3  
7.5  
ns  
ns  
ns  
SKEW  
t
TNK+ to DCLK (Note 6)  
Figure 8  
DCLK  
t
AD  
clock  
cycle  
Pipeline Delay  
PD  
Figure 8  
1
Note 1: Best-fit straight-line linearity method.  
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).  
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-  
mode input range (Figures 4 and 5).  
Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in V  
supply voltage,  
CC  
expressed in decibels.  
Note 4: The current in the V  
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-  
CCO  
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-  
ital outputs to a minimum.  
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).  
Note 6: t and t  
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a  
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-  
PD  
SKEW  
data bit. t  
DCLK  
itive load on the outputs is 15pF.  
_______________________________________________________________________________________  
3
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