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MA17501

更新时间: 2024-09-28 22:46:31
品牌 Logo 应用领域
DYNEX /
页数 文件大小 规格书
35页 433K
描述
Radiation Hard MIL-STD-1750A Execution unit

MA17501 数据手册

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MA17501
Radiation Hard MIL-STD-1750A Execution unit  
Replaces March 1997 version, DS4548 - 2.3  
DS4548 - 3.2 January 2000  
The MA17501 Execution Unit is a component of the Dynex  
Semiconductor MAS281 chip set. Other chips in the set  
include the MA17502 Control Unit and the MA17503 lnterrupt  
Unit. Also available is the peripheral MA31751 Memory  
Management Unit/Block Protection Unit. These chips in  
conjunction implement the full MlL-STD-1750A lnstruction Set.  
The MA17501 - consisting of a full function 16-bit ALU, 24 x  
16-bit dual-port RAM register file, 32-bit barrel shifter, 4 x 24-  
bit parallel multiplier, synchronisation clock generation logic,  
and microcode decode logic - provides all computational,  
logical, and synchronisation functions for the chip set. Table 1  
provides brief signal definitions.  
BLOCK DIAGRAM  
The MA17501 is offered in several package styles  
including; dual-in-line, flatpack and leadless chip carrier. Full  
packaging information is given at the end of the document.  
FEATURES  
MIL-STD-1750A Instruction Set Architecture  
Full Performance over Military Temperature Range  
(-55°C to +125°C)  
Radiation Hard CMOS/SOS Technology  
16-Bit Bidirectional Address/Data Bus  
16-Bit Full Function Registered ALU  
32-Bit Barrel Shifter  
24 x 16-Bit Dual-Port RAM File  
1.0 SYSTEM CONSIDERATIONS  
• 16 User Accessible General Purpose Registers  
• 8 Microcode Accessible Registers  
The MA17501 Execution Unit (EU) is a component of the  
Dynex Semiconductor MAS281 chip set. This chip set  
implements the full MlL-STD-1750A instruction set  
architecture. The other chips in the set are the MA17502  
Control Unit (CU) and the MA17503 Interrupt Unit (IU). Also  
available is the peripheral MA31751 Memory Management  
Unit/Block Protection Unit (MMU(BPU)).  
Figure 1 depicts the relationship between the chip set  
components. The EU provides the arithmetic and logical  
computation resources for the chip set. The EU also provides  
program sequencing logic in support of branching and  
subroutine functions. The lU provides interrupt and fault  
handling resources, DMA interface control signals, and the  
three MIL-STD-1750A timers. The EU and lU are each  
controlled by microcode from the CU. The MMU(BPU) may be  
configured to provide 1M-word memory management (MMU)  
and/or 1K-word memory block write protection (BPU)  
functions.  
4 x 24-Bit Parallel Multiplier  
• 48-Bit Accumulator  
• 16-Bit x 16-Bit Multiply in 4 Machine Cycles  
Instruction Pre-Fetch  
MAS281 Integrated Built-in Self Test  
TTL Compatible System Interface  
1/35  

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Mixer Diode, Very High Frequency, Silicon, NS-B1 PACKAGE-3