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M5-192/104-5AC PDF预览

M5-192/104-5AC

更新时间: 2024-02-11 08:00:18
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
47页 1091K
描述
Fifth Generation MACH Architecture

M5-192/104-5AC 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:144
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
最大时钟频率:91 MHzJESD-30 代码:S-PQFP-G144
专用输入次数:I/O 线路数量:104
端子数量:144最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 104 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK可编程逻辑类型:EE PLD
传播延迟:5.5 ns认证状态:Not Qualified
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

M5-192/104-5AC 数据手册

 浏览型号M5-192/104-5AC的Datasheet PDF文件第1页浏览型号M5-192/104-5AC的Datasheet PDF文件第2页浏览型号M5-192/104-5AC的Datasheet PDF文件第4页浏览型号M5-192/104-5AC的Datasheet PDF文件第5页浏览型号M5-192/104-5AC的Datasheet PDF文件第6页浏览型号M5-192/104-5AC的Datasheet PDF文件第7页 
Table 2. MACH 5 Speed Grades  
1
Speed Grade  
-10  
Device  
-5  
-6  
-7  
C
-12  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
-15  
C, I  
C, I  
I
-20  
2
M5-128  
C, I  
I
I
M5-128/1  
M5LV-128  
M5-192/1  
C
C
C
C, I  
C,I  
C, I  
C
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
I
I
I
I
2
M5-256  
C, I  
M5-256/1  
M5LV-256  
M5-320  
C
C
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C
C
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
I
I
I
I
I
I
M5LV-320  
M5-384  
C, I  
3
3
C
C, I  
C, I  
3
3
M5LV-384  
M5-512  
C
C, I  
C, I  
3
3
C
C, I  
C, I  
3
3
M5LV-512  
C
C, I  
C, I  
Note:  
1. C = Commercial grade, I = Industrial grade  
2. /1 version recommended for new designs  
3. Preliminary specificatons  
With Lattices unique hierarchical architecture, the MACH 5 family provides densities up to 512  
macrocells to support full system logic integration. Extensive routing resources ensure pinout  
®
retention as well as high utilization. It is ideal for PAL block device integration and a wide range  
of other applications including high-speed computing, low-power applications, communications,  
and embedded control. At each macrocell density point, Lattice offers several I/O and package  
options to meet a wide range of design needs (Table 3).  
1
Table 3. MACH 5 Package and I/O Options  
M5-128/1  
M5LV-128  
M5-256/1  
M5LV-256  
M5-320  
M5LV-320  
M5-384  
M5LV-384  
M5-512  
M5LV-512  
M5-192/1  
Supply Voltage  
100-pin TQFP  
100-pin PQFP  
144-pin TQFP  
144-pin PQFP  
160-pin PQFP  
208-pin PQFP  
240-pin PQFP  
256-ball BGA  
352-ball BGA  
5
3.3  
68, 74  
68*  
5
5
3.3  
68*, 74  
68  
5
3.3  
5
3.3  
5
3.3  
68  
68  
68  
68  
68*  
68*  
104  
104  
104  
120  
104*  
120  
104*  
120  
104*  
120  
104*  
120  
120*  
160  
120  
160  
120*  
160  
120  
160  
120*  
160  
120  
160  
160  
160  
184*  
192  
184*  
192*  
184*  
192*  
184*  
192*  
184*  
192*  
256  
184*  
192*  
256  
Note:  
1. The I/O options indicated with a “*are obsolete, please contact factory for more information.  
MACH 5 Family  
3

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