Datasheet > 存储 > 闪存> M29F002BB120P1

M29F002BB120P1

更新时间： 2024-01-26 19:42:46

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存存储内存集成电路光电二极管
页数	文件大小	规格书
22页	190K
描述
2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

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技术参数
数据手册

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M29F002BB120P1 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	0.600 INCH, PLASTIC, DIP-32	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.28
Is Samacsys：	N	最长访问时间：	70 ns
其他特性：	BOTTOM BOOT BLOCK	启动块：	BOTTOM
JESD-30 代码：	R-PDIP-T32	长度：	41.91 mm
内存密度：	2097152 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
类型：	NOR TYPE	宽度：	15.24 mm
Base Number Matches：	1

M29F002BB120P1 数据手册

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

BUS OPERATIONS

When Chip Enable is at V the Supply Current is

reduced to the TTL Standby Supply Current, I

CC2

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Table 5, Bus Operations, for a summary. Typically

glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not af-

fect bus operations.

To further reduce the Supply Current to the CMOS

Standby Supply Current, I , Chip Enable should

CC3

be held within V

± 0.2V. For Standby current

levels see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I

til the operation completes.

Automatic Standby. If CMOS levels (V ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

, for Program or Erase operations un-

CC4

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V , to Chip Enable

and Output Enable and keeping Write Enable

High, V . The Data Inputs/Outputs will output the

duced to the CMOS Standby Supply Current, I

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

CC3

value, see Figure 9, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Special Bus Operations

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require V to be applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Table 5, Bus Operations.

Block Protection and Blocks Unprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

able must remain High, V , during the whole Bus

Write operation. See Figures 10 and 11, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. For further information refer to Application

Note AN1122, Applying Protection and Unprotec-

tion to M29 Series Flash.

High, V .

Standby. When Chip Enable is High, V , the

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

Table 5. Bus Operations

Data

Address Inputs

Operation

Bus Read

Inputs/Outputs

Cell Address

Data Output

Data Input

Hi-Z

Bus Write

Command Address

Output Disable

Standby

Hi-Z

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

20h

Others V or V

B0h (M29F002BT)

B0h (M29F002BNT)

34h (M29F002BB)

A0 = V , A1 = V , A9 = V ,

Read Device Code

Others V or V

Note: X = V or V

5/22

1 2 3 456 7 8...22

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与M29F002BB120P1相关器件

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M29F002BB120P1T	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002BB120P3	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002BB120P3T	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002BB120P6	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002BB120P6T	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002BB45K1	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格

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