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M2062-11-669.1281LF PDF预览

M2062-11-669.1281LF

更新时间: 2024-01-25 01:34:13
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路
页数 文件大小 规格书
12页 458K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M2062-11-669.1281LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCN,针数:36
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.29JESD-30 代码:S-CQCC-N36
JESD-609代码:e3长度:8.99 mm
功能数量:1端子数量:36
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:3.1 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.635 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.99 mmBase Number Matches:1

M2062-11-669.1281LF 数据手册

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M2060/61/62, M2065/66/67  
Integrated  
Circuit  
Systems, Inc.  
VCSO FEC PLL FOR SONET/OTN  
P r e l i m i n a r y I n f o r m a t i o n  
HS/PBO Operation  
Optional Hitless Switching and Phase Build-out  
Once triggered, the following HS/PBO sequence  
occurs:  
The M206x Series is available with a Hitless Switching  
feature that is enabled during device manufacturing.  
In addition, a Phase Build-out feature is also offered.  
These features are offered as device options and are  
specified by device order code. Refer to “Ordering  
Information” on pg. 12.  
1.The HS function disables the PLL Phase Detector  
and puts the device into NBW (narrow bandwidth)  
mode. The internal resistor Rin is changed to  
2100k. See Narrow Bandwidth (NBW) Control Pin  
on pg. 6.  
The Hitless Switching feature (with or without Phase  
Build-out) is designed for applications where switching  
occurs between two stable system reference clocks. It  
should not be used in loop timing applications, or when  
reference clock jitter is greater than 1 ns pk-pk. The  
Hitless Switching sequence is triggered by the LOL  
circuit, which is activated by a 4 ns phase transient. This  
magnitude of phase transient can generated by the  
CDR (Clock & Data Recovery unit) in loop timing mode,  
especially during a system jitter tolerance test. It can  
also be generated by some types of Stratum clock  
DPLLs (digital PLL), especially those that do not include  
a post de-jitter APLL (analog PLL).  
2.If included, the PBO function adds to (builds out) the  
phase in the clock feedback path (in VCSO clock  
cycle increments) to align the feedback clock with  
the (new) reference clock input phase.  
3.The PLL Phase Detector is enabled, allowing the  
PLL to re-lock.  
4.Once the PLL Phase Detector feedback and input  
clocks are locked to within 2 nsec for 8 consecutive  
cycles, a timer (WBW timer) for resuming wide  
bandwidth (in 175 nsec) is started.  
5.When the WBW timer times out, the device reverts  
to wide loop bandwidth mode (i.e., Rin is returned to  
100k) and the HS/PBO function is re-armed.  
The LOL pin will indicate lock status on a cycle-to-cycle  
basis and may be intermittent until PLL phase lock has  
fully stabilized.  
When the M206x Series is operating in wide bandwidth  
mode (NBW=0), the optional Hitless Switching function  
puts the device into narrow bandwidth mode during the  
Hitless Switching sequence. This allows the PLL to lock  
the new input clock phase gradually. With proper  
configuration of the external loop filter, the output clock  
phase change complies with MTIE and TDEV  
specifications for GR-253 (SONET) and ITU G.813  
(SDH) during input reference clock changes.  
The optional proprietary Phase Build-out (PBO)  
function enables the PLL to absorb most of the phase  
change of the input clock during reference switching.  
The PBO function selects a new VCSO clock edge for  
the PLL Phase Detector feedback clock, selecting the  
edge closest in phase to the new input clock phase.  
This reduces re-lock time, the generation of wander,  
and extra output clock cycles.  
The Hitless Switching and Phase Build-out functions  
are triggered by the LOL circuit. For proper operation,  
a low phase detector frequency must be avoided. See  
“Guidelines for Using LOLon pg. 6 for information  
regarding the phase detector frequency.  
HS/PBO Sequence Trigger Mechanism  
The HS function (or the combined HS/PBO function)  
is armed after the device locks to the input clock refer-  
ence. Once armed, HS is triggered by the occurance of  
a Loss of Lock condition. This would typically occur as a  
consequence of a clock reference failure, a clock failure  
upstream to the M206x Series, or a M206x Series clock  
reference mux reselection.  
M2060/61/62 M2065/66/67 Datasheet Rev 0.4  
7 of 12  
Revised 30Jul2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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